I wish the team well, even though Gunnar has for some unknown reason got irritated with the Fpgaarcade team.
I've been pushing back a few fixes for the T68 soft core we currently use. There are potentially a few issues remaining with the 68020 mode,which are problematic to find.
I've developed a daughterboard with a real 68020 (and the rest of the AGA chip set) so I can run the soft cores against the originals and hopefully nail any functional / timing differences.
I am making some progress getting a public SVN mirror up, I expect this to be done in the next couple of weeks which will hopefully pacify some of the more zealous open source people in the community.
Anyhow, for me, 100% functional compatibility is the number one priority, followed by cycle accurate timing in 68000 mode. Then, maximum performance in 68020 mode.
I now have a functional model and microcode dump of a real 68K which is helping design a very lightweight new (open source) core.
One comment I will make (and please don't take offence Phoenix team) is I find it very unlikely you will be able to produce an ASIC. For my day job I design 28nm devices, and the mask costs are high. The cost of respins is high. I'm very open to helping out if you think it is doable.
Anyhow its a small community, lets all work and play together peacefully.
Cheers,
Mike
http://www.fpgaarcade.com