Motorola 68060 FPGA replacement module (idea)

[Plaz]

The best situation is that he release the HDL-resources. Other than that one could start with TG68 and work from there.

TG68 source looks like a good starting point, but if Yaqube is well on the way to creating the core needed, then wouldn't it be preferred to support that goal instead of duplicating the effort? Is his project so different in FPGArcade that it wouldn't work well here? I've not followed FPGArcade very closely, will the work be open or closed source?

Plaz

[freqmax]

It's hard to work with sources that you don't have

[billt]

I'll agree. Make it work FIRST. If it ships it's a bonus

The beauty with FPGA is that you can ship first, and code later

You gotta do something to prove the FPGA PCB works. No sense in shipping a buggy PCB and leaving the FPGA coders wondering why something doesn't work right... How do we do that? Put something in there and see if it can communicate with the host properly.

PCB things that could come out wrong:
shorts
opens
bad layer stackup choice making signal integrity a mess
bad signal angles can affect signal integrity as well as manufacturability (DFM)
mismatched trace lengths can affect timing

Opens and Shorts should be easy to check with a multimeter and a lot of patience. Ive had to do that before for boards containing 8 sockets for 700+ pin chips. A board like we're discussing here may not be quite that bad.

Timing and Signal Integrity issues are harder to check without running something at real-world speeds. There are expensive simulation tools that can probably a PCB layout as well, but I'm not sure if anyone here has and knows them. (If anyone does, please talk about that, I want to learn!)

While the 060 bus probably isn't the best example of something requiring obsessive-compulsive signal integrity planning, it is at the low end of where you start to care. The general rule of thumb for this starts around 50MHz. Some say they've seen problems as low as 17KHz...

So, how does one prove this PCB before shipping, to ensure it's worth putting hte "real" FPGA coding effort into?

[freqmax]

I'm thinking on developing at least one FPGA just to try it out. And you can't have the core until you have a PCB nor can you have a working PCB test until you have a core

So one make a PCB. Then generate a core that just toggle bits and does basic bus testing. When that is complete. The next step is to code a 68k core.

Perhaps it's possible to run the 68k bus really slow like 1 MHz just to prove it works.

[Heiroglyph]

TG68 source looks like a good starting point, but if Yaqube is well on the way to creating the core needed, then wouldn't it be preferred to support that goal instead of duplicating the effort? Is his project so different in FPGArcade that it wouldn't work well here? I've not followed FPGArcade very closely, will the work be open or closed source?

Plaz

With the CPU being on the same FPGA as the rest of the chips, he doesn't have to exactly duplicate the bus interface either so that's really only one part of the puzzle. (although a big one)

The A600 FPGA accelerator project is working on both bus and core, but for 68000.
http://www.majsta.com/

If the projects are both open then it's a good start.  For example, the A600 FPGA with an 020 core or use the 020 core and bolt on the A600 bus with updates to fit 680x0 bus specs.

[Heiroglyph]

While the 060 bus probably isn't the best example of something requiring obsessive-compulsive signal integrity planning, it is at the low end of where you start to care. The general rule of thumb for this starts around 50MHz. Some say they've seen problems as low as 17KHz...

I agree with everything you've said, but I have a question.

Why do we keep mentioning duplicating the 060 bus?

It's hard to find 060 CPU cards.
Real 060's have to be heavily adapted to fit the Amiga bus.

030 cards are dirt cheap and plentiful.

An 060 is no faster than a synchronous 030 with burst for communicating with the Amiga itself.  Actually they can often be slower since many 060's are async, can't burst, are running in 040 bus mode and have a lot of glue logic.

The 3000/4000 local bus are basically straight 030@25MHz, no glue required and I'd think the 1200 would be very similar but slower.  You can't talk to the Amiga faster than 25MHz, period.

Local devices on the CPU card can communicate any way you want them to.  They don't have to be limited to 030 Amiga speeds, they can be custom or off the shelf high speed buses.

030 just seems like the sweet spot for our needs.

[billt]

I agree with everything you've said, but I have a question.

Why do we keep mentioning duplicating the 060 bus?

Read the name of this thread's topic.

This started out as a discussion to replace the very difficult to find, legitimate, best mask-set, full-featured and fastest 68060 chips from Motorola/Freescale, to put into 68060 sockets such as the socket found on some Amiga accelerators and on MikeJ's daughtercard for FPGA-Replay system.

Other things, such as the 3000/4000 accelerator slot, 030 socket, 020 socket, 000 socket, etc. have also come up, and could most likley be used via adapter, or do new PCBs directly targetting those and reuse the FPGA softcore stuff there. No reason a TG68 or N050 or whatever can't be plugged into any one of those things, but this topic came from the 68060 issue and desire to have better than whatever it is we already have.

[freqmax]

Orignal problem: The FPGA Arcade has some 68020 hybrid. But the number of logic cells in the XC3S1600 is finite so any more fancy CPU has to be elsewhere. Now the solution mikej has accomplished is a daughterboard with a 68060 CPU.

However there's a small number of really fast 68060 CPUs and the numbers are declining. But if one use an FPGA instead of the CPU. One can create a replacement. And FPGA factors like type (Actel), blockram, HDL-code optimizations etc can improve the performance.

So the goal was to use it with FPGA Arcade. And A4000, A3000, A1200 etc is a bonus. A 68030 bus is a subset of 68060 so it won't provide 060 systems with a solution.

[Plaz]

It's hard to work with sources that you don't have

Shout out to Mr. obvious.

To the point..... has Yaqube ever mentioned opening the source?
For the answer to that, I guess I'll just go ask him myself. (predicting the answer is no)

Second question.... anyone know what detailed documentation is available for 060? Schematic of the internals would be the bomb.  I think I still have my 030 motorola dev books from back in the day. Guess I can start there.

Plaz

[JimDrew]

Has anyone worked with the MCC-216 hardware?  It uses an Altera Cyclone III in it.  I just received one with the developer package and wondered how this compares to what Mike is building.

[Heiroglyph]

Read the name of this thread's topic.

This started out as a discussion to replace the very difficult to find, legitimate, best mask-set, full-featured and fastest 68060 chips from Motorola/Freescale, to put into 68060 sockets such as the socket found on some Amiga accelerators and on MikeJ's daughtercard for FPGA-Replay system.

I understand the thread topic, but I think it's a flawed idea with a simple fix.  The 060 bus is more trouble than it is worth.  It's not the common denominator, it's an aberration.

Even 040 bus would be a better choice than 060.  Good 040 cards are really common and A3640's are like roaches.

It would be easier to make an 030 bus expansion board for the FPGA Replay and get more use out of the CPU work than just the people who are holding the remaining 060 cards for ransom.

Other things, such as the 3000/4000 accelerator slot, 030 socket, 020 socket, 000 socket, etc. have also come up, and could most likley be used via adapter, or do new PCBs directly targetting those and reuse the FPGA softcore stuff there. No reason a TG68 or N050 or whatever can't be plugged into any one of those things, but this topic came from the 68060 issue and desire to have better than whatever it is we already have.

If someone wants to pump years of work and thousands of dollars into an easily redesigned FPGA replay addon that a hand full of people own and the already hard to buy 060 cards, that's their time and money.  

It just doesn't make sense to me and I hope it doesn't take resources away from anything actually useful to the community.

[billt]

Shout out to Mr. obvious.

To the point..... has Yaqube ever mentioned opening the source?
For the answer to that, I guess I'll just go ask him myself. (predicting the answer is no)

Second question.... anyone know what detailed documentation is available for 060? Schematic of the internals would be the bomb.  I think I still have my 030 motorola dev books from back in the day. Guess I can start there.

Plaz

http://www.freescale.com/webapp/sps/site/taxonomy.jsp?code=68K

But understand that, making a replacement, all we really need are the bus spec and the instruction set, and any configuration/information registers in the original chip that a project such as this needs to reproduce. Anything else can be reimagined as we see fit, preferrably for the better.

[billt]

If someone wants to pump years of work and thousands of dollars into an easily redesigned FPGA replay addon that a hand full of people own and the already hard to buy 060 cards, that's their time and money.

Then let those interested in wasting their own time and money continue as they see fit. If you prefer an 040 or 030 or CPUslot or whatever, then do that or wait for something here to happen and port it down to your socket of choice. If you beat the 060 people, they can port yours up to the 060 bus. Not a big deal.

Also realize that the bus is probably one of the less difficult parts of this sort of thing. As the CPU core is the "hard part", various people could probably be designing different PCBs for diffeent sockets in parallel to the CPU core designer doing his thing. Regardless, any of these PCB people and bus people will probably be waiting on the CPU core people...

It just doesn't make sense to me and I hope it doesn't take resources away from anything actually useful to the community.

Different people have different opinions about what is and is not useful, is and is not a waste of time/money, etc. I don't agree that it is taking anything away from anything useful to the community. I don't agree that it's a waste of time, and some of us spend money to do things because we enjoy them, not to bring back a profit. No problems...

[billt]

Other stuff that may be interesting:
https://www.coursera.org/course/hardware
https://www.coursera.org/course/comparch
http://www.udacity.com/overview/Course/cs348/CourseRev/1

[freqmax]

Let's focus on the design rather than repeating the basics. Please?

[billt]

I'm thinking on developing at least one FPGA just to try it out. And you can't have the core until you have a PCB nor can you have a working PCB test until you have a core

So one make a PCB. Then generate a core that just toggle bits and does basic bus testing. When that is complete. The next step is to code a 68k core.

Perhaps it's possible to run the 68k bus really slow like 1 MHz just to prove it works.

Majsta at least got to 2MHz...

What PCB program will you use?