Motorola 68060 FPGA replacement module (idea)

[Heiroglyph]

It's not bit swapped, the high byte is in a different place but the bits of each byte are still in the same order.

03 E8 vs. E8 03

You do have to be aware of the size of the data though.  Reading/writing a sequence of bytes vs a sequence of words for example.

A sequence of byte data could be 03 E8 03 E8 and would not need swapping, you're reading each in order.

A sequence of word data would still be 03 E8 03 E8 but you need to know to swap based on the intended size so that it correctly reads as E8 03 E8 03.

Loading a register should swap on the read, so A0 would already point to the right location.  Once the data is in a register it's already swapped as needed based on the instruction used to read it.  Transfer between registers wouldn't need a byte swap.

[wawrzon]

We've recently seen the Prometheus PCI open sourced so there is a ZorroIII to PCI interface that works and only needs 1-2 CPLDs. It could be even simpler since there aren't multiple PCI devices, it would be a target not a host and you wouldn't need to multiplex the address and data lines.

i would design it though treating amiga like one had mounted pci device on a bus among possible others, being a pci gfx card for instance. of course there is rather no need to have dma between amiga and pci gfx card, its enough to have it between host cpu boad and pci. on the other hand michael boehmer (e3b) has improved prometheus firmware to enable amiga-pci dma but this is closed source due to his agreement with prometheus designers.

on subject of openpci or alternative standards, i would propose to coordinate effort with aros68k maintainers. aros team has considered and rejected openpci as its standard for various reasons (license, free availability, documentation). it provides pci hidd based partly on netbsd so far i know and in parallel a prometheus.library.

[freqmax]

you absolutely must have a cycle exact emulation.  There are quite a few programs that require it.

Which applications  require that besides A500 specific demos? it has been up before when Minimig were in the pipe. And there were some serious refutations on the issue.

What buses do SoC support? (ARM etc)

[Mrs Beanbag]

2 is added to the value of A0 and swapped.  This is no different than how we do it with software emulation.  An FPGA can certainly do anything that can be done in software.  Instead of the FPGA handling the entire CPU core, it would be handling the memory bus accesses and off-loading the CPU emulation itself to the primary (x86) CPU.

But then instead of getting "cdef" as the data, it gets "bahg" interpreted as "ghab" - completely wrong!

[Heiroglyph]

i would design it though treating amiga like one had mounted pci device on a bus among possible others, being a pci gfx card for instance. of course there is rather no need to have dma between amiga and pci gfx card, its enough to have it between host cpu boad and pci. on the other hand michael boehmer (e3b) has improved prometheus firmware to enable amiga-pci dma but this is closed source due to his agreement with prometheus designers.

on subject of openpci or alternative standards, i would propose to coordinate effort with aros68k maintainers. aros team has considered and rejected openpci as its standard for various reasons (license, free availability, documentation). it provides pci hidd based partly on netbsd so far i know and in parallel a prometheus.library.

I agree, although I'm 99% sure the Prometheus fix only fixed DMA between PCI cards.  The Prometheus isn't a master on both buses.

I thought the PCI hidd was reasonably close to or based on OpenPCI?  I seem to remember seeing headers from openpci in there a long time ago.

[wawrzon]

I guess you guys have to decide if you want 100% compatibility or not.  If you do, you absolutely must have a cycle exact emulation.  There are quite a few programs that require it.  You could also deliberately set emulation thresholds.  For example, you could set the speed/emulation type to be Amiga 500 (68000), Amiga 3000 (16MHz or 25MHz 030), Amiga 4000 (25MHz 68040), etc.  This way you could run those euro demos in Amiga 500 mode that won't work on anything else.  

speaking from a user perspective the idea of an accelerator absolutely contradicts anything being cycle exact, am i right? so neither is an a1200 cycle exact to a500 nor an amiga with any accel to the same device as such. i think its self explanatory we have to sacrifice cycle exactness. and as an owner of practically only accelerated amigas id say, this is a very good deal.

[Heiroglyph]

speaking from a user perspective the idea of an accelerator absolutely contradicts anything being cycle exact, am i right? so neither is an a1200 cycle exact to a500 nor an amiga with any accel to the same device as such. i think its self explanatory we have to sacrifice cycle exactness. and as an owner of practically only accelerated amigas id say, this is a very good deal.

That's what I was thinking also.  Anything that would break is already broken with existing accelerators.

[Bobo68]

So if those are too slow, then what about PCI?

PCI is faster than the Amiga bus both in clock and throughput and has the same bus width.  It should just be a matter of timing and translation.

We've recently seen the Prometheus PCI open sourced so there is a ZorroIII to PCI interface that works and only needs 1-2 CPLDs.  It could be even simpler since there aren't multiple PCI devices, it would be a target not a host and you wouldn't need to multiplex the address and data lines.

I've recently seen PLX PCI9054 which converts 060 to PCI bus and don't need CPLD/FPGA...

[wawrzon]

I thought the PCI hidd was reasonably close to or based on OpenPCI? I seem to remember seeing headers from openpci in there a long time ago.

im not sure. i remember i proposed incorporating openpci and been opposed on the dev ml.
the rudimentary 68k implementation is mostly by jason mcmullan, it doesnt even work yet, but allows to identify details of the present boards, at least in my mediator.

at the point when it becomes an issue you might join dev ml:
https://www.hepe.com/mailman/listinfo/aros-dev/
 or i will provide you with the mail address.

[wawrzon]

I've recently seen PLX PCI9054 which converts 060 to PCI bus and don't need CPLD/FPGA...

ermmm.. what? where?

[Bobo68]

ermmm.. what? where?

on ebay

[Heiroglyph]

I've recently seen PLX PCI9054 which converts 060 to PCI bus and don't need CPLD/FPGA...

It's not a direct drop in thing, you'd still need a CPLD or FPGA to take over as the CPU.  I'm really surprised nobody hooked one up to make a PCI backplane though.  There wouldn't be busmastering errors with a tested ASIC like this.  You'd still have trouble DMAing in and out of the backplane though.

Since we'd need to also spoof being the CPU, I figure a simple PCI target controller in the same CPLD/FPGA would be cheaper and not a lot of trouble.

Edit: I think those normally go for around $40 in small quantities.

[Mrs Beanbag]

What exactly are we trying to connect to what, in any case? I got lost somewhere along the line.

[freqmax]

@wawrzon, Any application that has failed for you because of accelerators ?

For buses in general:
 * Latency
 * Capacity (Mbit/s)
 * Electrical compability
 * Protocoll conversion

So I think PCI is doable but don't forget that translation between PCI and Zorro may introduce bottlenecks. But why introduce any bus at all between the CPU-in-FPGA and the CPU-socket? KISS..

[Bobo68]

I'm really surprised nobody hooked one up to make a PCI backplane though.

why nobody?
http://www.powerphenix.com/ctpci/english/overview.htm

[Heiroglyph]

@wawrzon, Any application that has failed for you because of accelerators ?

For buses in general:
 * Latency
 * Capacity (Mbit/s)
 * Electrical compability
 * Protocoll conversion

So I think PCI is doable but don't forget that translation between PCI and Zorro may introduce bottlenecks. But why introduce any bus at all between the CPU-in-FPGA and the CPU-socket? KISS..

I don't think FPGA alone is up to the task.  I think you'd get a slightly faster 060 at best and it would cost more than it's worth.

My proposal was to connect a current CPU of some kind to the Amiga bus as directly as possible and emulate an 030.

The directly as possible part is the big catch. PCI(-e) pretty much dominates the market these days, there aren't really any other good fast interfaces to new CPUs and not even that on the really cheap nice SOCs, you have to go up a notch to even get PCI(-e).