Motorola 68060 FPGA replacement module (idea)

[bloodline]

@ Heiroglyph

I'm concerned that USB (any flavour) will have too high a latency to be used for a CPU/Chipset bus, I'm gonna stick with my original idea of an SPI and see if I can make the numbers add up

[wawrzon]

I think if we've got some fast CPU running 68k emulation or otherwise, it would be a shame not to make its raw power available to the user in some way.

as is said i agree with heiroglyph on all points, especially on moldular construction and approach. see that jens schoenfeld is going exactly the same way now, providing unified interfaces for different computers and for different accelerators. perhaps it would even be possible to get him on boat, both adopting his interface standards, as advisor and as future manufacturer.
what concerns exposing the native cpu to the user, it might be done like on amithlon, as an option by a dedicated developer. that is the part of modular approach, we propose, that different concepts might coexist as long as there is enough interest there. btw why not invite bernd (umisef on aw.net) the amithlon coder as advisor too?

[freqmax]

I think an A1200 accelerator is worth doing with just an FPGA, some flash and some ram.
 
Making a 68060 socket compatible version might be useful for a minority, but I'm not convinced it's going to be very useful for the FPGA Arcade. It doesn't need a physical 68060 & it has an FPGA waiting for code.

For the A1200 you would then have to spin another PCB => more fuss.

There's a shortage of >75 MHz 68060 CPUs for the FPGA Arcade. And the FPGA on the base board isn't large enough to implement a 68060 properly.

I think A1200 and A3000 users could benefit from a plain mechanical adapter. And A4000 could benefit directly.

[wawrzon]

@ Heiroglyph

I'm concerned that USB (any flavour) will have too high a latency to be used for a CPU/Chipset bus,

im a noob, but likely..

here some thought interfacing via pci, seems doable, alas in german:
http://www.a1k.org/forum/showthread.php?t=35374&highlight=turbokarte&page=12

[Heiroglyph]

@ Heiroglyph

I'm concerned that USB (any flavour) will have too high a latency to be used for a CPU/Chipset bus, I'm gonna stick with my original idea of an SPI and see if I can make the numbers add up

That's cool with me, it would be way simpler if possible.  I've seen the opposite problem with SPI in my thought experiments, low latency but low throughput.

Maybe I'm shooting for to too much memory speed since I'm trying to match the best numbers I've seen.  Lower bandwidth might be acceptable.

The other option I've looked into a lot is being a PCI device.  It cuts out the ability to use really cheap SOCs, but many of the nicer ones (especially Freescale and TI) have PCI or PCI-e.  I don't think either latency or bandwidth would be a problem, even for ZIII, but the hardware cost would go up.

[bloodline]

That's cool with me, it would be way simpler if possible.  I've seen the opposite problem with SPI in my thought experiments, low latency but low throughput.

Maybe I'm shooting for to too much memory speed since I'm trying to match the best numbers I've seen.  Lower bandwidth might be acceptable.

Here is my thinking:

The PAL Amiga 500 has a CPU speed of 7.09Mhz, it only accesses the ram/chipset on every other cycle (effectively reducing the frequency to 3.545Mhz). With a bus width of 16bits, that means the highest data rate for the CPU/Chipset bus would be 6.76Meg per second.

A SPI bus with a frequency of 56.7Mhz can match that data rate, and I've used 80Mhz on an SPI bus with an SD card before, so bandwidth (at least for OCS/ECS) should be totally possible with SPI... Latency I guess will depend on how well the protocol is designed, but should be low

[Heiroglyph]

Here is my thinking:

The PAL Amiga 500 has a CPU speed of 7.09Mhz, it only accesses the ram/chipset on every other cycle (effectively reducing the frequency to 3.545Mhz). With a bus width of 16bits, that means the highest data rate for the CPU/Chipset bus would be 6.76Meg per second.

A SPI bus with a frequency of 56.7Mhz can match that data rate, and I've used 80Mhz on an SPI bus with an SD card before, so bandwidth (at least for OCS/ECS) should be totally possible with SPI... Latency I guess will depend on how well the protocol is designed, but should be low

But we've also got AGA machines with faster speeds and 32bit width.  All my numbers were based on the worst case A4000.

I figure if we can use it on a 4000, the others are a piece of cake.

[Mrs Beanbag]

Inside Out board made with Minimig-AGA, once Yaqube and friends have that finished up.

I never heard of Inside Out board, it seems to be a complete Amiga, CPU and all?

Don't really need the CPU on board. Just the graphics + sound.

[billt]

My issue with the FPGA/ARM combo chips is the price.

I've been trying to find a good way to interface the wave of super cheap ARM's that are 800-1200Mhz and loaded with peripherals.

It might take a combo chip, but then we're back to $1000 CPU cards.

Well, I'm just saying what I would do. Considering my available time, I'm not likely to. Anyone that might actually take up this sort of project is free to do things as they see fit. More than one are free to each do things their own way, which may have several different things happen.

My real dream is a 3000/4000 style accelerator card that's just an FPGA, memory and a bunch of connectors, including a Com-Express type 6 connector. Most other connectors would go to that, perhaps through the FPGA first for some muxing. Then that FPGA would be either a softcore 68k or a bridge to a ComExpress module, which could be PowerPC, x86, whatever. But I don't have time to do that either. I'm more likely to spend time on a PowerPC ComExpress module, which iealize as the best way to design OS4 "Amiga" motherboards today if we must stick with PPC. This 68060 direct replacement idea is an interesting diversion for the moment though.

[billt]

I never heard of Inside Out board, it seems to be a complete Amiga, CPU and all?

Don't really need the CPU on board. Just the graphics + sound.

Someone took the Amiga chipset and put it on an ISA (I think) card for a PC. I don't think it was around for very long, and I don't think there were very many of them.

[bloodline]

But we've also got AGA machines with faster speeds and 32bit width.  All my numbers were based on the worst case A4000.

I figure if we can use it on a 4000, the others are a piece of cake.

I fear you want to run before you can walk

If the SPI idea is cheap and simple, and if it works then you advance the design

[psxphill]

And the FPGA on the base board isn't large enough to implement a 68060 properly.

Has that been tried? I thought it was more that nobody had implemented the FPU & MMU.

[JimDrew]

I think we're having trouble understanding what you're suggesting, because you can't just convert a little endian processor to big endian using an FPGA.

Sure you can.  In fact, the FPGA would only swap certain instructions where this is required.

The swap is only required because the byte order is backwards (Endian issue).  So, if you fetch a long word from memory using something like mov.l $12345678,d0 that memory location will appear backwards to an x86 and would have to be swapped.  The swap occurs during the opcode emulation, and using some hardware means to perform the swap (like the bus wired backwards momentarily) would eliminate having to do it in software.

The problem with JIT is that it is not cycle exact, so it breaks a LOT of programs.  This is where the FPGA would come in handy as it could be used to throttle the instruction cycle speed so it is correct for a given desired performance level.

[utri007]

Could it be possible implement cpu and gpu to FPGA? Something like 68060 and Cirrus Logic GD5446 or S3 Virge? Picasso IV / Cybergraphics 64 3D

This way there would be possible get drivers, without hassle?

[Heiroglyph]

Has that been tried? I thought it was more that nobody had implemented the FPU & MMU.

I haven't seen a solution that is faster than a cheap 030 yet.  I've heard rumors of Natami, but haven't seen more than vapor.  Even that's not what I'd call significantly faster for the investment.

I also suspect that it's prohibitively expensive to get a sufficiently fast FPGA and few people are good enough to program it.

To me, using another CPU to emulate the instruction set puts you mostly in the realm of software where there are enough people with the skill to optimize the design.

[Bobo68]

Could it be possible implement cpu and gpu to FPGA? Something like ... Cirrus Logic GD5446 or S3 Virge?

whether their design is opened?