But if you tell the FPGA to create a gate, how does it do that? What is the FPGAs actual method of creating a gate inside itself? How does it remember that gate? What is actually going on at the physical level? Surely there aren't a lot of nano-bots building and tearing down hardware inside the FPGA.
OK, but you asked for it. :p This is a bigger question that you may have realized, but fasten your seatbelts for a quick & dirty lesson in the digital logic design that an "empty" FPGA chip actually is.
I seem to have surpassed the single post character limit, so I'll try and split this into two posts.
I'll use terms such as passgate (sometimes also called transmission gate), multiplexer, LUT (lookup table), flipflop, and maybe a couple other terms which I will not define here. For those that do not already understand their definitions, I'll leave them as research topics for you, but I'll give a little description of how they are built. Read elsewhere for more in-depth descriptions. But they are very basic digital design elements.
A passgate for example can be made from a single transistor, but they are often made from two transistors in CMOS technologies. It's a very simple switch, and either connects input directly to the output, or it separates the two ends from each other. To compare with other digital logic gates, a CMOS 2-input NAND gate is made of 4 transistors. A 2-input AND gate is likely made up of 6 transistors (basically a 4-transistor NAND followed by a 2-transistor inverter).
http://www.csee.umbc.edu/courses/graduate/CMPE640/Spring07/cpatel2/lectures/lect16_combo3.pdfA multiplexor can be made from a group of passgates, to make a sortof passive implementation, or it can be a stack of AND and OR and interter gates to make a more active output drive implementation.
http://en.wikipedia.org/wiki/MultiplexerA flipflop (slightly more complicated than a latch) is often a loop of storage elements with passgates in between, and when the clock sets the input side passgate to open or closed, this allows the flipflop input value to overdrive a different stored value in order to have the flipflop replace its previously stored value with the current input value.
http://en.wikipedia.org/wiki/Flip-flop_(electronics)
FPGA silicon is a fixes silicon array of logic elements with a lot of fixed wires between them. Each wire is a segment, not a complete path, but it is a length of metal drawn across the silicon.
A logic element is made up of a LookUp Table (commonly shortened to LUT for less typing), one or more flipflops, and a bunch of multiplexors and passgates, and SRAMS which store your design configuration.
The LUT is a small memory with some multiplexors on the output side. When the FPGA is configured on powerup, this memory is programmed to contain the output 1 and 0 values of the logic gate you want it to become. The inputs to your logic gate control multiplexors which select a particular bit of the memory, and the value of that memory bit is your 1 or 0 output value of your logic gate. I may have said in a previous post that the address bus of this LUT memory make up your logic gate inputs. If I didn't already correct that, the address to your memory is only used during configuration of what is held inside the memory. After configuration, the contents of this LUT memory are "fixed". Most FPGAs today are made from SRAM based LUTs, so they can be reprogrammed from one power cycle to the next to do different things, and this also allows possibility of reconfiguration while the system is on and running. (see Reconfigurable Computing) Older FPGA silicon designs used fuses (or anti-fuses which close when told to do so) to set the 1 and 0 logic values, and they were typically NOT changable. If you found a bug in your circuit design, you put that buggy chip in the trash and bought a new chip. A FLASH based FPGA may have small flash memory inside your LUT instead of SRAM, or it may have a FLASH storage on-die to contain your design bitstream file to be written to SRAM based LUTs.
The inputs of your LUT logic gate control the multiplexers on the output side of the LUT memory. They select which bit of the LUT memory is connected to the ouptut signal of your overall "logic gate". The bitstream configuration determines if bit 0 contains a 1 value or a 0 value, of bit 1 contains a 1 or 0 value, if bit 2 contains a 1 or 0 value, etc. The multiplexers do not know the contents of the LUT memory, they only connect the desired LUT memory bit to the output wire.
The output of your "logic gate" LUT goes to a flipflop, perhaps directly to more than one if you want to decide between rising edge clocking or falling edge clocking or perhaps other versions of flipflops that have clear or reset controls or not. Another multiplexor will select if the direct LUT output value is the ultimate output here, or if (one of) the flipflop output is the ultimate output of this logic element. If you have clear and/or reset controls on your flipflops, then even more multiplexors are used to select which wire connects to those signals. And even other multiplexors to select which wire connects to the clock of the flipflop, and perhaps if there is an inverter to the clock or not.
The various input bits of your logic gate are connected to multiplexors which make connections to the mass of wire endpoints available to your logic element. Lets say we have a 4-bit SRAM memory as our LUT memory.
To make your logic element (LUT + multiplexors + flipflop) "become" a 2-input AND gate, which has input wires A and B, and output wire D,
multiplexer 1 chooses between bits 0 and 1 of the LUT
multiplexor 2 chooses between bits 2 and 3 of the LUT.
multiplexor 3 chooses between the outputs of multiplexwrs 1 and 2. (I wish I could draw that schematic here)
write a 0 value into bit 0 of your LUT
write a 0 value into bit 1 of your LUT
write a 0 value into bit 2 of your LUT
write a 1 value into bit 3 of your LUT
a fixed 0 value is set to control multiplexor 1, so it is fixed to connect bit 0 to its own output.
select wire A to control multiplexer 2.
select wire B to control multiplexer 3. The inputs to multiplexer 3 are the outputs from multiplexers 1 and 2.
The digital logic truth table for a 2-input AND gate is:
A B | D
0 0 | 0
0 1 | 0
1 0 | 0
1 1 | 1
Multiplexer 1 is fixed to output the value of LUT bit 0.
When wire A is a 1 value input to multiplexer2 1, then it connects bit 3 to the output of multiplexer 1. If wire A is a 0 value, then it connects bit 3 to the output of multiplexer2.
When wire B has a value of 1, it connects multiplexer 2 output to the LUT output wire C. When wire B is a 0 value, then multiplexer 3 connects the output of multiplexer 1 to wire C.
So, if wire B is 0, then the value on wire A is irrelevant. B as a 0 tells multiplexer 3 to pass multiplexer 1 to output wire C, and multiplexer wire can only select LUT bit 0, which is contains value 0. This acrees with our truth table. (we could even set LUT bit 1 to a 1 and the truth table would still be correct, since bit 1 can never get out of multiplexer 1)
If wire B is a 1, then wire A can have an affect as multiplexer 2 is connected to output wire C. If wire A is value 0, then multiplexer connects bit 2 to output wire C, meaning it connects to bit 2 value of 0 to C. If A is value 1, then multiplexer 2 connects bit 3 to output wire C, meaning it is connected to the bit 3 value of 1 to C.
(to be continued)
