Sorry, bit behind with emails.
Update ...
Production is complete now. It is raining in Shenzhen and this is delaying the cardboard box delivery. The boards should be shipped out end of the week.
This means I get a little longer to keep playing with the core. It's all good though as I am working on fixing the cache and prefetch logic. The DRAM controller is designed for the daughterboard and has a 32 bit data path for efficiency. This means a bit of logic an endian-ness fiddling is required to attach it to the 68K softcore.
To fully test this, the VHDL testbench now loads an srec file directly into the DRAM at start up and I simulate the processor running with various tests, stalls, refresh etc.
/MikeJ