I'm (and many others) also happy to hear some news, or status report or planned roadmap 
(including 060 daughterboard, and new core).
Indeed, an update is due. No problems, just things are taking longer than I predicted - as usual.
The SMD production is complete, they are hand soldering the connectors etc. Waiting for boxes to be printed, but the boards should leave the factory by mid-week.
I'm taking advantage of the time to sort out some other aspects of the code.
Merging in some updates from other branches, testing the cache/prefetch logic with the new DRAM controller etc.
The codebase is a major change from the minimig project, large chunks are completely new and specific to the Replay board - as is the ARM controller firmware.
There are two reasons for this. One is to optimize and clean up the code for other cores - as much as possible should be common between the Amiga and Atari implementations for example. The other is to tidy up timing issues and get the compile time and area down. There are a lot of Xilinx optimizations, which will probably upset people as they can't just use the code on other boards - but my aim is to get the cleanest, fastest solution for my board.
Finally, building for production test, for example not just memory tests but eye scan so I can be sure the memory is working with good margin for voltage / temperature etc.
Finally, as I have completely re-written all the FD/HD/OSD code and protocol there is a bit of debug to be done there as well.
/MikeJ
