Perhaps I was not clear enough:
The info will not be processed using the "X86" processor but an EMULATED 680xx processor. For example:
Run emulator software on PC - It waits for a "Boot" signal from the amiga hardware, basically connected "In Place" of the 680xx cpu. When it sees this boot signal, same as the 68000 cpu it replaced, it will do exactly what the 68000 would.
I mean basically, you would have a connector shaped like the cpu your replacing. You would plug said connector in in place of the cpu. The emulator software would then provide the correct signals through a cable to this "Cpu" emulator, in essence allowing the pc to become the processor. Endian issues should NOT be a problem because the emulation knows what to expect, and will deal with it the same way that a 68000 would, ie basically the core of WINUAE etc. I mean, a 68000 basically is using +5v and 0 for signals. You would design a pc card or usb interface (If fast enough) that would do 2 things= read the +5v pins on the cpu connector that the amiga would put out, and in return set +5v or 0 on the pins that the amiga expects from the cpu. Thats the only connection a 68000 has to the amiga, a series of +5v and 0v, can be duplicated through this interface.
The card then digitizes? the +5v and 0 to provide data to the emulator, which then performs whatever op + memory operation the instruction says to do. Note, this is "Emulated" memory as well as op codes, so endian conversions should not have to occur, its all done with native signals from the amiga and then back out to the amiga.
Granted My hardware level understanding is not amazingly great, but basic, but here is how I see it:
Power on, PC sees +5v on a certain line, telling the amiga has been powered on. At this point, and I don't know the technicalities of it, it likely starts reading from the Amiga Rom chip for hardware level boot info. The pc just acts like the 68000.
Am I clear enough? Or am I explaining this wrong.
Karlos wrote:
amigaksi wrote:
>Such a design would be totally blighted by endian conversion issues. You'd probably need to use the big-endian memory access tricks they did for amithlon.
But he is suggesting some interface hardware in between to do the CPU signal translation in real-time.
How does this external converter know what size element is being accessed in order to do that?
The CPU core will perform byte/word/long/quad reads and writes on its own caches but the CPU as a whole will perform cache line transfers to/from the main memory. I can't see how any interface in between can have any way of knowing what the data being transferred is in order to to do any swapping. All it will see are long bursts of fixed width accesses.
