Minimig PCB run - interest thread

[Methanoid]

Xenepp, can we have an update on what is happening re building boards?

[TobiFlex]

source to an ATARI ST project that includes an almost finished 68K CPU

This CPU Core is not finish. The Debuging must go on. Currently hangs up this CPU Core with Kickstartrom 2.04 at #$F81914.

Viele Grüße
TobiFlex

[jkonstan]

 

TobiFlex wrote:

source to an ATARI ST project that includes an almost finished 68K CPU

This CPU Core is not finish. The Debuging must go on. Currently hangs up this CPU Core with Kickstartrom 2.04 at #$F81914.

Viele Grüße
TobiFlex

What set of Amiga hardware are you debugging the 68K VHDL CPU core with? Do you have an estimated clock rate for the 68K core in a Spartan3 FPGA ? I was going to try the 68K VHDL CPU core when I got my MiniMIG going.
Thank you for the update on it.


 :-)

[TobiFlex]

I have adapted the minimig Core to the DE2 Board from Terasic with a ALTERA Cyclone 2C35. With an external CPU MC68HC000 runs the Minimig perfekt. I have change the RAM Timing from SRAM to SDRAM - so i can use the on Board SDRAM Chip.

And now i use the Board to Debug Wolfgangs 68K Core.

[jkonstan]

TobiFlex wrote:
I have adapted the minimig Core to the DE2 Board from Terasic with a ALTERA Cyclone 2C35. With an external CPU MC68HC000 runs the Minimig perfekt. I have change the RAM Timing from SRAM to SDRAM - so i can use the on Board SDRAM Chip.

And now i use the Board to Debug Wolfgangs 68K Core.

Sounds as though you are using a stock FPGA evaluation/development board possibly with some adpater PCBs that you built.

More questions because I have a few evaluation FPGA boards as well ...
Q1) Did you build a PIC adapter PCB as Dennis had for the Spartan3 Eval board or did you use the Altera DE2 SD socket and write a bunch of code in order to replace the floppy ?
Q2) The current Verilog implementation on MiniMIG essentially runs 0 wait states with the external SRAM. Have you modified the MiniMIG Verilog core to allow for wait states so that SDRAM or DDR can be adapted ?
Q3) How do you find an affordable Altera DE2 ? Those are expensive unless you get the student discount ?


 :-)

[mongo]

Unless you can find or write a 68K core that can fit in the XC3S400 currently used by the MiniMig there is very little point.

To use Wolfgang's 68K core, you would need a much bigger FPGA.

Not much point replacing a $7 CPU when you need an FPGA that costs $20+ more to do it.

[jkonstan]

Since I have been busy working on trying to get a couple MiniMIGs put together, I have not yet compiled Wolfgang's 68K VHDL core; thus, I was not aware of its size in terms of Xilinx CLBs.

I agree completely that the 68SEC000 is pretty cheap $7 to $11; however, I was thinking more of getting around some of the present limitations of MiniMIG1:

1. The lack of more FPGA pins (soldering hobby/home project limit of 208 pin QFP on FPGA). The new extra FPGA pins could be used for IDE, Compact FLASH, parallel interface to Vinculum VNC1L (USB host controller with a CPU core and USB stack),  etc ....

2. The 68K bus clock rate limit on a two layer PCB. A larger Xilinx FPGA (more CLBs) with a soft 68K core embedded in it could possibly clock the soft 68K faster than the external 68SEC000. This would have to be investigated by compiling Wolfgang's VHDL code and running Xilinx timing analyser on it.

   :-)

[mongo]

jkonstan wrote:

1. The lack of more FPGA pins (soldering hobby/home project limit of 208 pin QFP on FPGA). The new extra FPGA pins could be used for IDE, Compact FLASH, parallel interface to Vinculum VNC1L (USB host controller with a CPU core and USB stack),  etc ....

2. The 68K bus clock rate limit on a two layer PCB. A larger Xilinx FPGA (more CLBs) with a soft 68K core embedded in it could possibly clock the soft 68K faster than the external 68SEC000. This would have to be investigated by compiling Wolfgang's VHDL code and running Xilinx timing analyser on it.

   :-)

There are enough free pins on the FPGA to do IDE as it is with a few external components and Compact Flash can also be connected via the IDE port.

Wolfgang's 68K core will run up to about 17 MHz in a Spartan 3.

The easiest was to gain more I/O pins is to change to a Spartan 3E. The design changes are minimal, you can still use the same 208 pin QFP package, and you gain more gates and more I/O pins.

[tonyyeb]

I wish i had the foggyest what you lot are talking about. It all sounds very impressive all this tech speak! I only know software... and nothing low-level  :-(

[TobiFlex]

Q1) Did you build a PIC adapter PCB as Dennis had for the Spartan3 Eval board

No.

or did you use the Altera DE2 SD socket and write a bunch of code in order to replace the floppy ?

Yes.

Q2) The current Verilog implementation on MiniMIG essentially runs 0 wait states with the external SRAM. Have you modified the MiniMIG Verilog core to allow for wait states so that SDRAM or DDR can be adapted ?

I use SDRAM. With DDR I have no experience. The SDRAM Clock is 112MHz. The SDRAM and the minimig runs synchron.
The SDRam needs 8 Clocks to read or write one Data word. This is a half CPU Clock. That enougth time to access.

Q3) How do you find an affordable Altera DE2 ? Those are expensive unless you get the student discount ?

 
This is my secret ;-)

Viele Grüße
TobiFlex

[jkonstan]

mongo wrote:
There are enough free pins on the FPGA to do IDE as it is with a few external components and Compact Flash can also be connected via the IDE port.

I agree that Spartan3E is better way to go on an update to MiniMIG.

I have implemented several IDE interface in Verilog over the years; thus, I am pretty curious. There are 4 spare FPGA spare I/O pins left in MiniMIG1. How do you intend to support/implement an IDE interface (IDE_RESET, CS0*, CS1*, INTRQ, DMREQ, DMACK, IORDY, IORD*, IOWR*, ICS16*, DASP*, DA0-DA2, DB0-DB15) which require at least 12 FPGA I/O pins and some external CBT16245 level shifters used on 68K bus ?

Also, I was not thinking of using the compact FLASH card in IDE mode (where Pin9 is pulled to ground and only good for compact flash memory cards).  My thought was to have a compact flash socket that was actually supported compact flash peripheral cards as well such as ethernet and serial port cards (i.e. Full Compact FLASH socket mode = PCMCIA with reduced number of address lines).

 :-)

[freqmax]

Any better fpga than the XC3S500E would require the use of a BGA socket.

As for benefits of a soft 68k core one is that supply just won't end. So it might be worthwhile to make debug and refine it. But maybe wait with using it until non-bga FPGAs become cheap and dense enough to accomodate it.

[mongo]

jkonstan wrote:


I agree that Spartan3E is better way to go on an update to MiniMIG.

I have implemented several IDE interface in Verilog over the years; thus, I am pretty curious. There are 4 spare FPGA spare I/O pins left in MiniMIG1. How do you intend to support/implement an IDE interface (IDE_RESET, CS0*, CS1*, INTRQ, DMREQ, DMACK, IORDY, IORD*, IOWR*, ICS16*, DASP*, DA0-DA2, DB0-DB15) which require at least 12 FPGA I/O pins and some external CBT16245 level shifters used on 68K bus ?

Address and Data lines connect to the 68K via level shifters, same with the Reset line. IORD*, IOWR* CS0*, and CS1* can easily be generated completely externally, though you can reduce the number of external components if you use one output line of the FPGA as a IDE Chip Select line. IORDY has to go to the FPGA for it to generate wait states for the 68K if needed, but even that might not be totally necessary unless you plan on using a really old drive. INTRQ has to go to the FPGA, unless you want to poll the drive instead of using interrupts, but I don't recommend doing that if you don't have to.

DMARQ, DMACK, ICS16*, and DASP* aren't needed.

3 FPGA I/O pins and a few external components are all that are required.

[freqmax]

mongo wrote:
Wolfgang's 68K core will run up to about 17 MHz in a Spartan

How many % of the fpga logic does it use?
Which Spartan were used?, esp which speed grade -4 or -5 ?

Page 7 (of 208)
http://direct.xilinx.com/bvdocs/publications/ds099.pdf

[Doobrey]

TobiFlex wrote:
I have adapted the minimig Core to the DE2 Board from Terasic with a ALTERA Cyclone 2C35. With an external CPU MC68HC000 runs the Minimig perfekt.

Any idea if Freescale's 68306 would work fairly easily? ( straightaway I can see some work needed to convert IPL2:0 to the 306's separate IRQ lines).

Looks like its built in DRAM controller would make adding upto 64MB pretty easy, plus there's some programmable chip selects and IO pins for extra hackable goodness :hammer:

[jkonstan]

Doobrey wrote:

Any idea if Freescale's 68306 would work fairly easily? ( straightaway I can see some work needed to convert IPL2:0 to the 306's separate IRQ lines).

Looks like its built in DRAM controller would make adding upto 64MB pretty easy, plus there's some programmable chip selects and IO pins for extra hackable goodness :hammer:

MC68306 could work since it is based on the 68HC000 core.
This is a nice idea (especially with the JTAG port on the MC68306); however, the MC68306 would have issues. The MC68306 DRAM controller works only with old obsolete DRAM which is no longer produced anymore. MC68306 is a 5Volt I/O part; thus, we would have to use level shifters between 5V MC68306 <=> 3.3V FPGA. Thus, there is not as much benefit in using MC68306 as we would like.

 :-)