Hey all-
I think most of you are on-target here for the question, but I'll summerize.
The basic issue around existing chips is ONLY Agnus/Alice. There are internal and external limits to memory addressing on any device.
For the external world, on the chip bus, there are actually two: the limits on the system address bus to Agnus/Alice (how much of the CPU bus can the chips see) and the limits to addressing of the memory chips themselves on the multiplexed DRAM bus. Internally, there's the secondard issue of how much memory Agnus/Alice can directly access in DMA.
The reason upgrades were possible at some point in time was simply that these two didn't match. It was fairly easy, for instance, when going from thin Agnus to Fat Agnus, to allow a larger CPU and memory address bus.. that was all new logic, and kind of on the periphery of the chips (in the thin Agnus circuitry, much of this stuff was done in the system, not the chip anyway).
So an Agnus chip might allow CPU access to 1MB of memory, but only 512K of that could actually be chip memory, since the internal addressing counters in Agnus only supported 512K of address space. Once you had a similar design with more bits for actually memory addressing directly by Agnus/Alice, all of that addressed memory could be chip RAM. If you added more address bits still, that wouldn't help, since then the external interfaces would be limited in address space (much like the 68000 was logically 32-bit inside, but only brought out 24-bits worth of address space).
It's only Agnus/Alice in question, due to the way the chip work together. Agnus is generating all of the chip RAM addresses, regardless of what's happening on the chip bus. Sometimes, it's a memory cycle from the main CPU, sometimes it's a display fetch or audio cycle, sometimes a blit cycle, etc. In conjunction with the memory address bus there's the register access bus (RGA bus), which is seen by Paula and Denise/Lisa.
The specific register access code tells the whole chip bus what kind of access this is. Sometimes, it's Agnus or the CPU writing to a register physically located in another chip, which means there's no DRAM cycle at all. On a video fetch, for example, the memory access will be put out from Agnus's video counters, and the RGA code tells Denise to read the DRAM bus and shift that value into one of the bitplane shift registers. Same idea with Paula accesses... all of the memory access/counting stuff takes place in Agnus or Alice. So that's the one chip that would need to change if you wanted more chip memory.
Even AAA worked much the same, with the Andrea chip doing the Alice/Agnus piece. There was some additional complexity, like dealing with the line buffer chips (Linda), the ability to handle VRAM or dual Linde/Monica pairs to support a 64-bit graphics bus (the graphics data bus wasn't always the same as the main chip databus), but the basic idea was similar.
In an emulator, of course, you can try to perfectly emulate an existing Amiga chip, but there's no reason you can also emulate chips that never existed. If it's a simple thing, like more Chip RAM, the OS already supports it, maybe with a little help (eg, it may not detect 8MB automatically, but it knows what to do with it when it's there).
The 8MB/2MB jumper in the A4000 was put in there based on the identical jumper in the A3000+. When we were working out the last details of the AA chipset (we == me, Bob Raible, Victor Andrade, and George Robbins), Bob was building Lisa in CMOS, Victor was doing Alice in NMOS. The NMOS design limited the changes that could be made ... Agnus was already close to the limits of that technology. We hoped to be able to do a followup AA+ with a CMOS Alice, and if so, that was going to handle at least 8MB of Chip RAM. So we stuck the means for that into the early design, and we (meaning mostly Greg Berlin and Scott Schaeffer, with a little of my help) carried it forward into the A4000. But there was never a chip built that could use it.
If someone built an add-on that could perfectly replicate the function of the custom chips, there no reason they couldn't support 8MB of Chip RAM, of course. However, this is inherently a hack, because the only place you can all the signals needed to replace the three chips is at the chip bus itself. You'd have to physically replace the custom chips, you couldn't do this on a Zorro card, at least not without big software changes (interrupts you can't generate on the expansion bus, things like that).
-Dave
