Your first link states that this book cannot be used.
It can be used, but be aware of performance penalties. Most X86 desktops includes a working cache coherency hardware.
The point is caching did affect self-modifying code on later than 8088 processors (not just Pentium I/II) but they are still considered backward compatible.
AMD K8 (which includes Northbridge) keeps the instruction and data caches coherent in hardware, which means that a store into an instruction closely following the store instruction will change that following instruction. Other processors, like those in the Alpha and MIPS family, have relied on software to keep the instruction cache coherent. Stores are not guaranteed to show up in the instruction stream until a program calls an operating system facility to ensure coherency. The idea is to save hardware complexity on the assumption that self-modifying code is rare.
The reason why AMD K8 includes additonal hardware complexity is to support for self-modifying X86 code.
For Intel Core 2, Errata AW46 i.e.
"Self/Cross Modifying Code May Not be Detected or May Cause a Machine Check Exception"
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
I assume you know about Intel micro-code patches.
This issue was fixed in E0 and R0 stepping.
AW = "Intel® Core™ 2 Duo processor E8000 series".