Any opcode that would cause an exception on a real 680x0 cpu can be used by software as a virtual opcode. LINEA & LINEF were officially available for that, but it's certainly possible that a piece of software could rely on any exception. The MMU & FPU that is proposed is certainly incompatible.
Actually, it is a bit more complicated. Line-A is certainly not available for new opcodes as this line is taken, both by MacOs (operating system traps) and also by Atari TOS (the blitter).
The F-Space is partially available. Motorola has the standard 68882 FPU mapped there, and the MMU, and some extended instructions of the 68060/040 map here.
Besides that, some new functions can at least cause problems, e.g. a new set of data registers or a new address register. Problem is that these are not saved and restored by the exec scheduler. Thus, the scheduler would need to be patched. But then, a couple of utilities depend on the stack frame of the scheduler, thus you can either continue to use these programs and not make use of the new registers, or use the registers and get rid of the programs.
Actually, I personally would rather get rid of the extra registers as I consider the Amiga "market" too small for such an experiment.
Anyhow, all these are engineering arguments, but my central point is not even related to engineering. I don't want to repeat this all over again.