Die space for m68k on FPGA?

[matthey]

The whole point of parallel decodes is that you can decode the first and second at the exact same time. If you have to look at the first to see what the length is, then you've failed. You need fixed length, then you can split the instruction cache so that odd/even instructions can be accessed simultaneously.

The Superscaler 68060 averages better than 1 instruction per cycle. A good assembler programmer should be able to average about 2 instructions per cycle in some code. This means that the 68060 is able to decode in parallel with variable length instructions. Short and simple instructions are the key. ARM with Thumb 2 also uses variable length instructions (Thumb 1 used a 16 bit instruction mode only).

Thumb2 sounds slower:

...

• The best Thumb-2 is -O3 -funroll-loops -mthumb -march=armv7-a -mtune=cortex-a8 at 88.7% of overall best

...

I agree that Thumb 2 is a little slower. ARM Holdings claimed 15-25% slower but I am guessing that did not consider that the code is in the cache more often. The figure above is more realistic and good enough that Thumb 2 is used most of the time. Thumb 2 is a real ISA that can stand on it's own unlike Thumb 1. Newer ARM processors will likely drop Thumb 1 support and maybe more.

With PPC we can run powerup/warpup software, implementing arm is boring.

The fpga Arcade has an ARM CPU so there is no need to emulate. PPC would be interesting but fpga PPC CPU performance would be lousy.

[freqmax]

The ARM CPU on the FPGA Replay is most likely busy serving the FPGA with disc emulation and doesn't have the code space to do much else. The transfer capacity to the FPGA may also be a serious bottleneck.

[danbeaver]

I thought I read that FPGA was meant as a way of prototyping a complex circuit so you you don't waste silicon making prototypes that don't work. Once you have your working FPGA you then lay it into a faster more economical silicon. The reason for keeping it in FPGA is that it can be changed if needed.

Any hint as to the truth in this rumor?

[Hattig]

I thought I read that FPGA was meant as a way of prototyping a complex circuit so you you don't waste silicon making prototypes that don't work. Once you have your working FPGA you then lay it into a faster more economical silicon. The reason for keeping it in FPGA is that it can be changed if needed.

Any hint as to the truth in this rumor?

Why do you call it a rumour? It's one of the use cases of an FPGA.

Howevermaking an ASIC is really expensive. For small quantities of logic you may implement using an FPGA even in the end product.

[psxphill]

The Superscaler 68060 averages better than 1 instruction per cycle. A good assembler programmer should be able to average about 2 instructions per cycle in some code. This means that the 68060 is able to decode in parallel with variable length instructions.

68060 can despatch two instructions at the same time, I don't think it decodes them at the same time.
 
"The superscalar micro-architecture actually consists of two distinct
parts: a four-stage instruction fetch pipeline (IFP) responsible for
accessing the instruction stream and dual four-stage operand execution
pipelines (OEPs) which perform the actual instruction execution. These
pipeline structures operate in an independent manner with a FIFO instruction
buffer providing the decoupling mechanism."
 
I don't believe it can sustain 2 instructions per cycle for long before the fetch pipeline runs dry & that is if you can even find worthwhile work to do in instructions that can run in parallel.
 

The ARM CPU on the FPGA Replay is most likely busy serving the FPGA with disc emulation and doesn't have the code space to do much else. The transfer capacity to the FPGA may also be a serious bottleneck.

Even so, the ARM is a SOC. If you want to use it for emulation then you'd need to be able to configure it's memory map. Maybe you could do it with MMU tricks, but it's not really in the spirit of the FPGA arcade.

[ChaosLord]

better would be to add specific instructions to the 68k that help with emulation of other processors.

+99999

[freqmax]

Which will cause incompatabilities..

[psxphill]

Which will cause incompatabilities..

Yeah, any design that allows you to write software that won't run on a real amiga is very bad thing. Anyone who wants something new would find a PC more suitable, you could even run AROS on it.

[ChaosLord]

68060 can despatch two instructions at the same time, I don't think it decodes them at the same time.

The M68060 dispatches, decodes, executes, completes and writes the results of 2 instructions at the same time.

This applies to most of the common simple simple instructions.

It does not apply to gigantic complicated instructions or rare instructions.

Furthermore, it does 3 instructions at the same time, as long as 1 of the instructions is a correctly predicted branch.   Loops are common structures of computer programming.  The branch at the bottom of the loop will be correctly predicted the 2nd thru the nth times it is executed.

I don't know if it will correctly predict the LOOP branch the 1st time it is encountered.  But if you have a loop from 1 to 1000 then it will be correctly predicted 999 times out of 1000 which is a fairly good rate.

[ChaosLord]

Add some new instructions.

Which will cause incompatabilities..

Intell adds new instructions all the time.

Yet I never see you posting on Intel forums "omg!  Its incompatible!"

p.s. Never ever ever ever buy a Rosewill keyboard.  This stupid thing @#?!@>#$ up every single msg I type.  GRRRR.  It only worked for 25 days.  Since then its been complete crap.

[ChaosLord]

Yeah, any design that allows you to write software that won't run on a real amiga is very bad thing. Anyone who wants something new would find a PC more suitable,

You said "any design that allows you to write software that won't run on a real amiga is very bad thing."

This means PCs are bad because its a design "that allows you to write software that won't run on a real amiga"

Then you tell ppl to buy a PC.

You are not making any sense.

[ChaosLord]

The FPGA used in Replay is not likely to have the die space to handle 386 + m68k at the same time.

386s are dirt cheap.  NewEgg was selling 2Ghz Celerons with a free springloaded keyboard for $25.00 last week.

As for 386 it has been discussed before. The size is just too big to be practical. It's way better to use the ASIC 386 until moores law makes it feasable.

[asymetrix]

a quick look on opencores : http://opencores.org/project,ao68000

Features

CISC processor with microcode,
WISHBONE revision B.3 compatible MASTER interface,
Not cycle exact with the MC68000, some instructions take more cycles to complete, some less,
Uses about 4750 LE on Altera Cyclone II and about 45600 bits of RAM for microcode,
Tested against the WinUAE M68000 software emulator. Every 16-bit instruction was tested with random register contents and RAM contents (Processor verification). The result of execution was compared,
Contains a simple prefetch which is capable of holding up to 5 16-bit instruction words,
Documentation generated by Doxygen (http://www.doxygen.org) with doxverilog patch (http://developer.berlios.de/projects/doxverilog/). The specification is automatically extracted from the Doxygen HTML output.
WISHBONE compatibility

Version: WISHBONE specification Revision B.3,
General description: 32-bit WISHBONE Master interface,
WISHBONE signals described in IO Ports,
Supported cycles: Master Read/Write, Master Block Read/Write, Master Read-Modify-Write for TAS instruction, Register Feedback Bus Cycles as described in chapter 4 of the WISHBONE specification,
Use of ERR_I: on memory access – bus error, on interrupt acknowledge: spurious interrupt,
Use of RTY_I: on memory access – repeat access, on interrupt acknowledge: generate auto-vector,
WISHBONE data port size: 32-bit,
Data port granularity: 8-bits,
Data port maximum operand size: 32-bits,
Data transfer ordering: BIG ENDIAN,
Data transfer sequencing: UNDEFINED,
Constraints on CLK_I signal: described in Clocks, maximum frequency: about 82 MHz.
Use

The ao68000 is used as the processor for the OpenCores aoOCS project - Wishbone Amiga OCS SoC (http://opencores.org/project,aoocs)
It can also be used as a processor in a System-on-Chip booting Linux kernel version 2.6.33.1 up to init program lookup (System-on-Chip example with ao68000 running Linux).
Similar projects

Other free soft-core implementations of M68000 microprocessor include:

OpenCores TG68 (http://www.opencores.org/project,tg68) - runs Amiga software, used as part of the Minimig Core,
Suska Atari VHDL WF_68K00_IP Core (http://www.experiment-s.de/en) - runs Atari software,
OpenCores K68 (http://www.opencores.org/project,k68) - no user and supervisor modes distinction, executes most instructions, but not all.
OpenCores ae68 (http://www.opencores.org/project,ae68) - no files uploaded as of 27.03.2010.
Limitations

Microcode not optimized: some instructions take more cycles to execute than the original MC68000,
TRACE not tested,
The core is still large compared to other implementations.
TODO

Optimize the desgin and microcode,
Count the exact cycle count for every instruction,
Test TRACE,
Write more documentation.
Status

April 2010: Tested with WinUAE software MC68000 emulator,
April 2010: Booted Linux kernel up to init process lookup,
December 2010: Runs as a processor in OpenCores aoOCS project,
January 2011: Core area optimization by over 33% (Thanks to Frederic Requin).
July 2011: Project copied to (https://github.com/alfikpl/ao68000). Further development of ao68000 will continue on github.
Requirements

Icarus Verilog simulator (http://www.icarus.com/eda/verilog/) is required to compile the tb_ao68000 testbench/wrapper,
Access to Altera Quartus II instalation directory (directory eda/sim_lib/) is required to compile the tb_ao68000 testbench/wrapper,
GCC (http://gcc.gnu.org) is required to compile the WinUAE MC68000 software emulator,
Java runtime (http://java.sun.com) is required to run the ao68000_tool (ao68000_tool documentation),
Java SDK (http://java.sun.com) is required to compile the ao68000_tool (ao68000_tool documentation),
Altera Quartus II synthesis tool (http://www.altera.com) is required to synthesise the soc_for_linux System-on-Chip (System-on-Chip example with ao68000 running Linux).

[Fats]

Better would be to add specific instructions to the 68k that help with emulation of other processors.

For the use case of running DOSBox in AmigaOS on an FPGA, I personally think it is more efficient to get rid of the whole complex JIT emulation in the first place. Of course just a matter of opinion.

greets,
Staf.

[psxphill]

You said "any design that allows you to write software that won't run on a real amiga is very bad thing."
 
This means PCs are bad because its a design "that allows you to write software that won't run on a real amiga"
 
Then you tell ppl to buy a PC.
 
You are not making any sense.

I'm glad you admitted that you don't understand my point. It proves beyond any doubt just what I've been dealing with.
 
I'd explain it, but you either couldn't understand or you are trolling.
 

The M68060 dispatches, decodes, executes, completes and writes the results of 2 instructions at the same time.

It's pipelined, while it can dispatch an instruction in 1 clock cycle and execute an instruction in 1 clock cycle. They aren't the same instruction that it's doing, you don't notice that from the point of view of the program until you get a mis-predicted branch.

[ChaosLord]

DosBox with 68k Dynamic Recompilation should be able to achieve 386 emulation speeds on a fast 68060 or fpga 68k CPU. The bonus is that the Amiga can multitask at the same time kind of like the advantage of ShapeShifter over a real 68k Macintosh.

+9999

An enhanced fpga 68k CPU could support faster emulation of x86 by providing some useful instructions and addressing modes that the x86 has but the 68k does not.

Adding new instructions is easy.  Adding new addressing modes.... uhmm... you would just have to say that certain instructions are hardwired for this new addressing mode that you want?