I just received my shiny new (ok, used) HP16700A Logic Analyzer with the 16715A modules which gives me over 200 channels of lovely 667mhz/167mhz sampling.
Of course, my favorite DUT is an A500.
I'm struggling with knowing which clock to use for which busses for state mode sampling.
One of things I'm looking at is watching disk dma.
I'm having trouble seeing the strobes happen on the RGA, so that I can measure off the strobes to find the appropriate times to watch the databus for the corresponding DMA slots. Based on the chart, it looks like starting around the 8th time slot (8*280ns from strobe, right?) I should see the disk data.
Ideally, I want to watch the flux pulses arrive on DKRD, watch Paula signal Agnus on DMAL for the transfer, and then grab the corresponding data on the 16-bit databus.
What clock should be used to sample RGA[8:1] ? Someone suggested in an unrelated post that sampling on the rising edge of CDAC(I think a shifted 7mhz clock off 7M) when CCK=1 should be used. But Paula only has access to CCK and CCKQ clocks coming in. My weak understanding is that there is a fixed known phase relationship between the clocks, so Paula could always use say both edges of those clocks to derive a clock it doesn't have direct access to.
What's the nominal values I should be seeing on RGA? Mostly 0x3C's(STRHOR) and 0x3E's(STRLONG) and some 0x38's(STREQU) and 0x3A's(STRVBL)?? And the MSB for RGA is RGA[8], right?
Most of the documentation I've read says that everything is synchronous to CCK. Is the rule of thumb to use CCK unless otherwise needed?
I banged my head last night until pretty late trying to figure this out -- I could really use the help.
I currently have Paula and all of the clocks available on Agnus hooked up.
Thanks.....
kamiga
