@karlos
I agree with you regarding JIT. I have thought about doing something along those lines.
ColdFire does support address register indirect with scaled index and 8-bit displacement.
The limits are that the index register only supports longword and that the scale can be
1, 2 or 4 (8 only supported if you have an FPU).
move.l (a0,d0.w*4),d1 ....... illegal
add.w #4,a1 ................. illegal
move.l (a0,d0.l*4),d1 ....... ok
It took a little while for me to modify my assembler habits, but I'm used to it now. With
V4 they added byte and word extensions back to the cmp instruction and added a few more
such as:-
mov3q.l #5,(100,a0,d0.l*4) .. move 5 longword extended to destination
............................. length of operand + extension = 32bits
mvs.b (a0),d0 ............... move byte , sign extended to long
mvz.b (a0),d0 ............... move byte , zero extended to
............................. mvs.w and mvz.w also supported
sats d0 ..................... signed saturate, sets max/min(overflow)
intouch (a0) ................ prefetch instructions into cache
Motorola have even added some interesting ones to the V2 core (MCF5282):-
bitrev d0 ................... bit reverse (31..0)<->(0..31)
byterev d0 .................. byte reverse (endian modify)
ff1 d0 ...................... find first one in register
strldsr #val ................ push sr to stack, then load new sr
Regards,
Stephen.