FPGA for dummies

[freqmax]

Machines that adhere to the same electrical specification as the "original" is real.

The missing masks, and original code just shows how bad proprietary designs are for long term usage. But that's the way it is, like it or not. Someone could scan the orignal chips (don't throw them!). But such process is still hard. So the method that remains is reverse engineering.

Does anyone know how the orignal designs were managed?, I know 6502 was done with manual methods like pen and papper, OCS used logic chips and wire-wrap. But somewhere after that they ought to migrated into some electronic design system.

[bloodline]

I'm remembering in an interview that the AGA design had a few bugs in it that needed reworking on the motherboard (sorry can't remember te exact source right now)... But suffice to say, you wouldn't want the original logic network of the AGA... It would be better to use a new circuit built to the correct specification

[Britelite]

it's interesting to note:  on the Amiga and c64 demoscene, i can cite a few examples of new demos (created after fpga blueprints for these systems) which push REAL hardware to the limit yet run fine on real machines. yet, because they do not play nicely with documented hardware timings and such - the code breaks fpga "hardware" and software emulatrs.

Please do name a few of these (new) demos.

[psxphill]

Loading it repeatedly would cause corrupted memory, but I guarantee no two systems would see the same corruption pattern. An FPGA simulation using the same memory would behave in the same way. Normally we make our lives easier and use memory controllers which work, or SRAM - so you wouldn't have to worry about this particular problem.

Saying that you won't get this particular problem proves my point that what you doing with an FPGA is emulation. You pick the behaviour that you want to implement and produce a simulation of it.
 
Software could use this to detect that it's not running on real hardware, or software could use the random corruption as entropy for a PRNG.
 
You can't implement DRAM in an FPGA that will behave similar to 1980's memory when operated out of spec (i.e. not refreshed).

[Fats]

Saying that you won't get this particular problem proves my point that what you doing with an FPGA is emulation.

Are you claiming using an FPGA is always emulation ?
Is an FPGA based Cisco router emulation then ? What are they emulating, are you also in the league that says this is emulating a fictional hardware implementation that never will be manufactured ?

greets,
Staf.

[mikej]

Saying that you won't get this particular problem proves my point that what you doing with an FPGA is emulation. You pick the behaviour that you want to implement and produce a simulation of it.
 
Software could use this to detect that it's not running on real hardware, or software could use the random corruption as entropy for a PRNG.
 
You can't implement DRAM in an FPGA that will behave similar to 1980's memory when operated out of spec (i.e. not refreshed).

Um, well it depends. If you attached the same DRAM to the FPGA Z80 core, you would get exactly the same behaviour. We could produce a better model of the DRAM by having an access counter per bit, and a pseudo random decay scanner - so yes with enough effort you can do it.

My point is, the Amiga core chipset is 1) fully sync so the underlying logic structure matters not one bit, and 2) so small and simple it is easy to get it pretty much totally accurate.

If you were to take the same netlist and produce a modern 65nm ASIC say, then the timing for that would be further off than the FPGA copy - but all three devices would be functionally interchangeable.

/MikeJ

[Thorham]

Is an FPGA based Cisco router emulation then ? What are they emulating, are you also in the league that says this is emulating a fictional hardware implementation that never will be manufactured ?

You have to look at what the FPGA does here (I didn't ). Is it something that can be ASICed, or is the functionality of the FPGA used in a different way?

[hairy]

Um, well it depends. If you attached the same DRAM to the FPGA Z80 core, you would get exactly the same behaviour. We could produce a better model of the DRAM by having an access counter per bit, and a pseudo random decay scanner - so yes with enough effort you can do it.
/MikeJ

It might be even simpler, unless aiming for "virtual analog" DRAM modeling

By chance (a bug), I've observed the failed refresh behaviour of a fast page SIMM, and it's amazing how much stuff is still intact after A FULL MINUTE.
So while a small bunch of cells might (or not) fail shortly after the time listed in the datasheet, the number grows much slower than I imagined, no avalanche effect!

All seems to indicate that decay of cells happen with an exponential rate (linked to capacitor discharge curve vs internal noise, I guess).

So probably a couple of LFSRs, a few counters, and some other glue might be sufficient, expecially if the CPU probing for failed refresh is a relatively slow 8-bitter.

[hairy]

You have to look at what the FPGA does here (I didn't ). Is it something that can be ASICed, or is the functionality of the FPGA used in a different way?

Is mostly done in FPGAs because you can update both the CPU firmware and the HW accel functions. Still economically viable considering the cost of midrange and high end routers.
IIRC high end switchrouters (6500 and 12000) also use ASICs.

The functions offloaded to hardware is progressively increasing with the class of the router.
In some midrange models (3600) you can see the effect of FPGA vs CPU processing by using standard vs extended access lists (in reasonably massive amount ).

(recalled from faded memories, please feel free to correct me)

[psxphill]

Are you claiming using an FPGA is always emulation ? Is an FPGA based Cisco router emulation then ?

No, which is why I said "what you are doing with an fpga"
 

What are they emulating,

An Amiga, the emulation is good enough to run Amiga software.
 

are you also in the league that says this is emulating a fictional hardware implementation that never will be manufactured ?

No, don't know what you're getting at there but it seems irrelevant to the discussion of emulating 68k based Amiga hardware.
 

We could produce a better model of the DRAM by having an access counter per bit, and a pseudo random decay scanner - so yes with enough effort you can do it.

I know you can do it, but that would count as simulation & emulation. Which is my main point.

[freqmax]

All seems to indicate that decay of cells happen with an exponential rate (linked to capacitor discharge curve vs internal noise, I guess).

Likely related to the threeshold of the internal sense amplifiers. Ie before it reaches the thermal noise floor.

[HenryCase]

Even an FPGA & ASIC running from the same VHDL don't necessarily behave the same way due to clock skew.

ASICs don't run VHDL to function. You obviously don't know what you're talking about, perhaps a book would help. Here are Jeri Ellsworth's recommendations:
https://www.youtube.com/watch?v=kobf8IOB0oA

[psxphill]

ASICs don't run VHDL to function. You obviously don't know what you're talking about, perhaps a book would help. Here are Jeri Ellsworth's recommendations:
https://www.youtube.com/watch?v=kobf8IOB0oA

It's ok, I know about baking an ASIC from VHDL.
 
Running is a perfectly acceptable term for operating a circuit.
 
I guess you misunderstood what I meant, those books might come in useful.

[psxphill]

Likely related to the threeshold of the internal sense amplifiers. Ie before it reaches the thermal noise floor.

Yeah good luck with converting that 1:1 in an FPGA.

[HenryCase]

It's ok, I know about baking an ASIC from VHDL.
 
Running is a perfectly acceptable term for operating a circuit.
 
I guess you misunderstood what I meant, those books might come in useful.

A baked ASIC STILL doesn't run VHDL, again would suggest you do a bit more research.

[psxphill]

You take the VHDL & it gets turned into an ASIC. I know how that works. Once you have the ASIC you run it when the clock starts. Running doesn't require a CPU style fetch execute mechanism, just a clock.
 
I understand whats going on physically in the FPGA and ASIC & it supports my argument about using an FPGA to recreate an Amiga is simulation/emulation.
 
I am not going to explain everything in minute detail, just so you can't find a way to purposefully misinterpret what I'm saying.
 
"It is difficult to get a man to understand something, when his salary depends upon his not understanding it" Upton Sinclair.