To give you an example, in the 6502 some of the "undefined op-codes" are a result of an incomplete decode PLA. What happens is some internal nets are undefined, and we can tell from the design if they are likely to float in one direction (high or low). Then, we get the same behavior. If it is unpredictable then different 6502 devices will also behave in different ways.
In the 6502 case it is mostly predictable, in other chips there may be other entropy that makes it harder to predict. As soon as you have to work out if they are likely to float in one direction or the other & adjust the VHDL accordingly, then you cannot be using the original circuit 1:1.
The side effects of an NMOS circuit are going to be different to that of a CMOS circuit. Even an FPGA & ASIC running from the same VHDL don't necessarily behave the same way due to clock skew.
It might meet the same documented ratings for timing etc, but that is meaningless when even trying to simulate something so it behaves exactly the same way when operated out of spec (which often is the case for undocumented side effects).
It wouldn't suprise me if you hadn't seen any of these issues on the Amiga, it was a pretty simple design that has had very few exploitable undocumented effects. However there are many other platforms where that is not the case and hopefully you'll get to those eventually.
Something like the Z80 R register, which is a read/write random register. However it's not really random because it's the ram refresh register. Loading it repeatedly can cause your memory to not be refreshed, so bits randomly drop out if the memory is not read by the CPU. I'd love to see how an accurate FPGA simulation of that would work.