That simply means AGA is a new version of the Amiga chipset.
Wait a minute, are the Amiga custom chips done in ASICs? Aren't ASICs chips that can be programmed once?
Indeed. As long as it's clear that it's a philosophy and not necessarily set in stone.
The Commodore custom chips were probably GateArrays. (I think I even saw/heard somewhere that the name for the Gary chip is simply an abbreviation for "GateArray") But this is again symantics, as marketing people at chip companies make up new words for essentially the same thing when an old word becomes to sound as if it must represent old technology to their customers.
An ASIC is a hard-wired chip. Application-Specific Integrated Circuit. The circuit design is turned into a gate level letlist (OR gates, AND gates, inverters, passgates, muxes, etc) and they are placed onto the die and then connected by metal wires and vias. That's a "Custom chip". It's custom manufactured to be exactly what the customer wants, and nothing else.
GateArray was a word to describe one way to complete an ASIC. In GateArray, there are different sizes of die, so smaller customer designs don't waste a horrible amount of die space, and large designs can be put into a large die. The logic area is a "sea of gates", in that a very regular pattern of transistors are laid down, available for use, and wafers are likely already manufactured up to that point. Then the customer design is really just a custom set of metal and via masks to connect things together. Where an OR gate was placed, the transistors on the wafer are connected by metal to complete that OR gate. If that location was an AND gate, then those transistors are connected by metal to complete an AND gate. Any gate locations not used will have transistor silicon p[resent, but tied off to be non-functional, and instead will likely become capacitors on the power bus. (gate to the source/drain area under the gate is essentially a capacitor in all CMOS transistors) It's a metal-programmable method, in that no particular circuit of any kind exists until metal wiring is fabbed to define one.
Then there is Standard Cell, the word that came after GateArray sounded "old". In Standard Cell, things are really only a minor difference to GateArray. Standard Cells have more customization per logic gate layout, and they do not have the very regular structure underneath. but you can lay down rows of logic gates, and include some extra things beyond the actual design, in case an error is found then you might (hopefully) be able to use some of those extras to fix things with a metal-mask only change later. While logic gate placement in Standard Cell doesn't give the super-generic underlayer structure that Gate-Array does, it can still be considered a metal-programmable technique. As far as what we chip designers do to make a Standard Cell ASIC die design, it's exactly the same thing(s) we do to make a GateArray style ASIC.
ASSP, or Application Specific Standard Product, is another term for ASIC, with some particular marketing meaning to it. it, like an ASIC by name, is a custom chip designed for one and only one application. The marketing terminology difference is that a customer may not be abel to afford to have his design made exclusively for himself and no one else. But it's important he gets it. So he can get the ASIC made, but the fab house is able to sell it to other customers in addition to the original customer. The original customer gets a discount this way, and is one way for a smaller company to get a custom chip made when he otherwise cannot afford such a thing.
SoC, System On a Chip, is an ASIC. It'll go through the same design steps and go through the same kind of fabrication as any other ASIC/custom chip using that fab process. The SoC ARM processors in your cell phones are ASICs.
Flash memories are ASICs, at least at my employer. It only adds a few layers to the wafer manufacturing process. SRAM chips are ASICs. FPGAs are even ASICs. The last FPGA silicon designs we did here were using the ASIC group design flow. Even before that, the more custom layout was also an ASIC, in that the specific application the integrated circuit was to be, was an SRAM-based FPGA. Then we added a microcontroller on the same die, and had a programmable System On Chip, and that itself was an ASIC too.
An ASIC does not get "programmed". It gets manufactured. And as soon as the last layer of the wafer is manufactured onto it, it gets cut into individual die, put in a package, and that's your final complete chip. Nothing comes after that except testing, shipping, and PCB assembly.
