Exactly. In an emulation there's all kinds of things happening in the background to just to enable to make what is being emulated work. The real thing doesn't require any of this overhead at all.
It's like a software emulation: An emulated computer needs a computer and software, while the actual computer works fine by itself.
Hmmm. What do you think is "happening" in the background of an FPGA design? Once it's configured, all that is fixed. Configuration 1's stay 1's, and configuration 0's stay 0's. The configuration memories to not change. There is no controller going down the address bus doing read or write accesses, not changing any values. The multiplexer settings which control the signal routing are fixed, they do not change and move wire connections around while the system is on. There's overhead stuff "present" and taking up space, but it's not "doing anything", or "nothing is happening there". It's "just there" at that point.
In an ASIC, does it make a difference if I use a library cell carrying the name D flipflop which serves the function of a D flipflop, or if I do an ECO design change, have no empty spaces to put another "real" D flipflop library cell that I somehow forgot, and have to combine a handful of NAND gates that I do have room for here and there, in order to effect a D flipflop function instead? Or, oh crap, that NAND gate should have been an AND gate. The AND (6 transistors) is too big to directly replace the NAND gate (4 transistors), but I have room over there for an inverter. Do a NAND plus an inverter emulate an AND gate, or implement it in an ASIC?
It's like a software emulation: An emulated computer needs a computer and software, while the actual computer works fine by itself.
An emulated computer needs software. Some group of instructions that are continuously fetched from one of several types/levels of storage somewhere, decoded, ALUed, reading values from parameters and writing values to register or memory destinations, in order to effect the target opcode format, ALU, instruction decode, registers, memory map, etc. In what way do you think this activity is continuously occurring in the FPGA underneath your logic circuit?
And another thought about "fixing" an FPGA. We'd once looked into but never sold a metal mask fixation option for our FPGAs, which would replace the configuration SRAMS and the LUT memory with metal hardwired 1's and 0's, should a security concerned customer want to do that to get a fixed die design instead of going through the effort of ASIC conversion. If I had a Minimig core designed to work well in my FPGA, and I did this metal mask replecement, most of the die is the same as the reprogammable FPGA, all those multiplexors are still there exactly the same way, but I can no longer change their controls, have I de-emulaterified this metal hardwired thing?