Strange how my day job get's discussed on an amiga site
I am working in a design services group and mainly do projects for ESA.
The key to radiation hardening is to use larger process sizes. Although it makes your transistors bigger and therefore increasing the chance of a particle hit, it decreases the effective amount of charge that particle can dump into the silicon comprising your transistor, thus reducing the chance of a bit flip. Basically, the smaller your components, the more vulnerable they are to the damaging effects of ionization. The second thing you need to do is harden the chip circuitry itself, eg putting ECC on everything.
That's only half of the story. You are talking about so-called 'single events', e.g. one particle that disrupt the logic in the circuit. It is true that larger process nodes are less sensitive for single events due to higher capacitive loads reducing the effects of a particle. But still you need to design for single events for example in the 0.18um node I am mostly using. ECC on the memories you already mentioned. For the registers, there are designs with redundancy built in so that if a particle impacts on one side of the register the other redundant side takes cares that the state of the register is not changed.
Also filters can be applied so that a signal is only taken if it lasts for a certain time. Effects caused by particle impacts only last for a certain time and they will be filtered out in this way.
Another technique is triple redundancy. e.g. you put each logic function three times on the chip and when one path gives another result than the other two paths, you discard the former.
Another technique is using silicon-on-insulator (SOI) where transistors are actually put on top of an isolator (actually AMD 65nm and 40nm is SOI) and not made in the bulk silicon wafer itself. This reduces significantly the volume where the particles interact with the transistors and often removing most of the single events.
Another aspect of radhad design is total ionizing dose (TID). Particles that impact on a chip can cause particles be trapped in the isolating materials of a chip. This will cause the performance of the transistors to drift with the TID put on a chip. And here the bigger technology nodes are more sensitive as the gate oxides are thicker. Smaller nodes have thinner oxides (only few nm) almost removing the TID effect on the transistors.
The biggest reason space agencies are conservative about technology nodes is that it takes a lot of testing and money to qualify a certain node for space applications and thus designers stick to already qualified processes.
hope this was interesting,
Staf.
