A 68EC060 should work fine, shouldn't it? You might be missing the MMU and FPU but you still have the TTR registers to map out cache-inhibited regions and also FPU emulation libraries.
As far as I am aware, the resolution of the TTR registers is 16MB minimum, so the best scenario would be to map the lower 24 bits of address space, including chipram and custom chipset registers as cache-inhibited, serialised access.
Fortunately since the hardware is very flexible we can map all the other nice fast ram outside that range and mark it as fully cached and copyback enabled.