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Earlier results show 256 byte instruction- and data cache improves performance to twice that of A4000 68040 @ 25 MHz. Dhrystone 9868, MFlops 10.30 measured with sysinfo.
You mean Mips=10.30 not MFlops right? There's probably not room to add FPU support in the fpga although it would only take 4 FPU instructions to do well in the SysInfo MFlops test. I posted the SysInfo FPU MFlops test on the Natami board...
http://www.natami.net/knowledge.php?b=2¬e=35355The SysInfo tests are a joke. SysSpeed is a little better.
Are Natami team open to this as well, or are they a closed-project group wanting to do their own thing?
I think they are open to standards for 68k ISA enhancements and (S)AGA/RTG enhancements. It would mean more software would support it. Software needs to support enhancements to get a benefit from them. More than 1 CPU standard could be supported if it's too burdensome to add full support. For example, a 68CF standard could add ColdFire instructions only and 68CF2 could add more enhancements for example. A defined specification, name with which to specify it and willingness of developers to support it is what is needed. I would be willing to help if I could find enough interest. I think developers that would support it include the Natami Team, Frank Wille (vasm, vbcc) and me (new version of ADis disassembler and also worked with Frank on some CF optimizations for vasm including more to come). Rune Stensland may do a Asm-Pro update as well. The 68k is a great development platform and we can make it better with a little bit of effort and cooperation.
1 block ram is about 2K byte. This is quite sufficient as a cache in this case.
Even a 2k cache will cause trouble for poorly written games using self-modifying code. Can the cache size be changed or is there bus sniffing (snooping)? I believe the N68k will get bus sniffing eventually in order to have as large of caches as they want.