Reading through a few comments on here. As far as I understood it PPC has a smaller instruction set than x86 and like for like will run much faster than an x86.
PowerPC G3 has more instructions than Pentium II i.e. refer to
http://arstechnica.com/cpu/4q99/risc-cisc/rvc-5.html---
From
http://en.wikipedia.org/wiki/Reduced_instruction_set_computingA common misunderstanding of the phrase "reduced instruction set computer" is the mistaken idea that instructions are simply eliminated, resulting in a smaller set of instructions. In fact, over the years, RISC instruction sets have grown in size, and today many of them have a larger set of instructions than many CISC CPUs.[6][7] Some RISC processors such as the INMOS Transputer have instruction sets as large as, say, the CISC IBM System/370; and conversely, the DEC PDP-8 – clearly a CISC CPU because many of its instructions involve multiple memory accesses – has only 8 basic instructions, plus a few extended instructions.
The term "reduced" in that phrase was intended to describe the fact that the amount of work any single instruction accomplishes is reduced – at most a single data memory cycle – compared to the "complex instructions" of CISC CPUs that may require dozens of data memory cycles in order to execute a single instruction.[8] In particular, RISC processors typically have separate instructions for I/O and data processing; as a consequence, industry observers have started using the terms "register-register" or "load-store" to describe RISC processors.
Some CPUs have been retroactively dubbed RISC — a Byte magazine article once referred to the 6502 as "the original RISC processor" due to its simplistic and nearly orthogonal instruction set (most instructions work with most addressing modes) as well as its 256 zero-page "registers". The 6502 is no load/store design however: arithmetic operations may read memory, and instructions like INC and ROL even modify memory. Furthermore, orthogonality is equally often associated with "CISC". However, the 6502 may be regarded as similar to RISC (and early machines) in the fact that it uses no microcode sequencing. However, the well known fact that it employed longer but fewer clock cycles compared to many contemporary microprocessors was due to a more asynchronous design with less subdivision of internal machine cycles. This is similar to early machines, but not to RISC.
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The Concept of the Instruction Set Architecture from
http://arstechnica.com/cpu/2q00/x86future/isa-future-2.htmlRISC vs. CISC: the Post-RISC Era from
http://arstechnica.com/cpu/4q99/risc-cisc/rvc-1.htmlRISC and CISC, Side by Side from
http://arstechnica.com/cpu/4q99/risc-cisc/rvc-5.htmlRISC vs. CISC Conclusion from
http://arstechnica.com/cpu/4q99/risc-cisc/rvc-6.htmlBoth the Athlon and the P6 run the CISC x86 ISA in what amounts to hardware emulation, but they translate the x86 instructions into smaller, RISC-like operations that fed into a fully post-RISC core. Their cores have a number of RISC features (LOAD/STORE memory access, pipelined execution, reduced instructions, expanded register count via register renaming), to which are added all of the post-RISC features we've discussed. The Athlon muddies the waters even further in that it uses both direct execution and a microcode engine for instruction decoding. A crucial difference between the Athlon (and P6) and the G4 is that, as already noted, the Athlon must translate x86 instructions into smaller RISC ops.
