Zorro 3 Bus Speed

[Crumb]

I'd overclocked my A500 back in '89 with a 32 MHz crystal. It did work nicely but my RGB monitor was literally screaming from the increased scan rate - and the integrated clock was running quite fast.

Zorro3 can be overclocked to 33Mhz too but real amiga video and sound will probably suffer.

[Zac67]

Zorro3 can be overclocked to 33Mhz too but real amiga video and sound will probably suffer.

Hmm - Zorro III doesn't actually have a clock, it's all asynchronous...

[Effy]

So it seems perfectly possible to install a jumper that allows you to run the 33 Mhz once the drivers for gfx card and sound card are loaded so the standard video and sound won't be used anymore ?! I thought the way to do this was to use a slower crystal and not faster ...

[Zac67]

So it seems perfectly possible to install a jumper that allows you to run the 33 Mhz once the drivers for gfx card and sound card are loaded so the standard video and sound won't be used anymore ?! I thought the way to do this was to use a slower crystal and not faster ...

How's overclocking the chipset supposed to have any impact on Zorro III operations? Zorro II might be another story since its clock is derived from the 28 MHz clock, but Z3 is much faster anyway.

And how does a slower crystal speed up things???

[trekiej]

One of the parts of the Asynchronous 68000 bust transfer is the wait states that are added while waiting for /DTACK. /DTACK can be created by a counter that is activated by /AS which is active low Address Strobe. The clock counts for a number of cycles then applies /DTACK.
What is also interesting is the circuits used to interface SDRAM. The address gets multiplexed by a counter to do the two sets of address reads, that is from the cpu to sdram. This is done after /AS and before /DTACK.

[trekiej]

What is nice about Asynchronous timing is that the cards can work at different speeds.
*
DMA, and then CPU accessing the the PIC's memory maybe where the clock comes in to play, to speculate.

[tnt23]

One of the parts of the Asynchronous 68000 bust transfer is the wait states that are added while waiting for /DTACK. /DTACK can be created by a counter that is activated by /AS which is active low Address Strobe. The clock counts for a number of cycles then applies /DTACK.

It could be worth mentioning that /DTACK cannot be generated by a counter or just at will. For reads, /DTACK is asserted by the slave to indicate that the valid data is on the bus. For writes, the /DTACK is again asserted by slave as soon as it has latched the data from the bus. That's why writes from CPU to external memory can be faster then reads.

[Tension]

One of the parts of the Asynchronous 68000 bust transfer is the wait states that are added while waiting for /DTACK. /DTACK can be created by a counter that is activated by /AS which is active low Address Strobe. The clock counts for a number of cycles then applies /DTACK.
What is also interesting is the circuits used to interface SDRAM. The address gets multiplexed by a counter to do the two sets of address reads, that is from the cpu to sdram. This is done after /AS and before /DTACK.

Yet another post that goes right over my head  

Excellent.

[trekiej]

@ tnt23
What I am refering to is that a memory chip does not or appear to not have that ability but a PIC ( add-on card )does/could. I do not know of any SDRAM chips that have ability, the author did not specify that.

The author shows a counter that counts to a specified amount of time and aserts a /DTACK. The counter is started by /AS. It appears that it does not guarantee that data has made it safely.

I believe that there is a situation after so many wait-states that under the right circumstances the read/write can be repeated. That is something I have to look up.

I am not trying to say that the wait is arbitrary. Looking at the timing diagram, I believe 3 things can happen, success, bus error, or repeat.
Sure, from /AS to /DTACK is X number of cycles for which this would all happpen.

I hope this clears up what I mean.

[tnt23]

@ tnt23
What I am refering to is that a memory chip does not or appear to not have that ability but a PIC ( add-on card )does/could. I do not know of any SDRAM chips that have ability, the author did not specify that.

The author shows a counter that counts to a specified amount of time and aserts a /DTACK. The counter is started by /AS. It appears that it does not guarantee that data has made it safely.

Sorry I must have completely missed the design you guys discuss. I thought it was about speeding up Zorro cycles by automating /DTACK generation.

[Crumb]

@Zac67

I mean overclocking the entire motherboard. Perhaps just the buster part could be overclocked, I don't know. My friend Frank Brana overclocked his A2000 denise (and fried a pair of them) and got 31Khz video (but he told me demos didn't look good)

[trekiej]

No problem, I need to further investigate where the clock comes in to play.
Before studying the 68000 the clock is/was used to time everthing, it seems, at least in appearance, that one could get away with using R/W and ENable lines for timing.
That is me speculating.

[Zac67]

I mean overclocking the entire motherboard. Perhaps just the buster part could be overclocked, I don't know. My friend Frank Brana overclocked his A2000 denise (and fried a pair of them) and got 31Khz video (but he told me demos didn't look good)

Buster runs off the CPU clock, so raising that would overclock the CPU section and Buster. The chipset section has its own (28 MHz) clock and runs asynchronously.

Overclocking will speed up things (like CPU, bus, ...) while getting you closer to the edge. Once you've exhausted the tolerances in your system and exceeded the inherent speed limit you're outa luck and crash the system. On the 3000 the probable first point of failure is the SCSI adapter - don't try with your 'good' drive.

Depending on whether the Z3 bus is the bottleneck for a given operation and how the PIC copes with the higher speed, your system might get faster - or not.

IMHO, a much better approach to speeding up the system is to look at current limits. E.g. I've been told that you can significantly speed up motherboard fast RAM by using 50 ns or 'very good' 60 ns RAMs and setting Ramsey to 16 MHz mode, thus bypassing a wait state. Probably this would also speed up Z3 DMA and PIO operations.

[trekiej]

@Zac67
You know more about that than I do, humble grin.
As far as I can tell, and to speculate, to slow the system down to get more performance reminds me of an accordion effect.
The accordion effect is like a string of cars going over a speed bump. They get bunched up at the speed bump. Then they pick after the speed bump. It is as fast as the slowest chip or function.
IMHO, lol

[Zac67]

Hmm...

Actually lowering a clock speed can't speed up anything (apart from the rare occasion where you profit from a quicker sync on asynchronous bus operations).
The only thing speeding up might be perceived speed in the case of slowing the stopwatch while not changing the speed of the actually gauged hardware. That would be the case if you underclock the chipset while keeping the same CPU speed.

[trekiej]

I was wandering if I should answer the above post.
Here goes, I do not buy PC hardware except for those rare times I buy PC hardware.
That is how it sounds.