Finally, a flash game for hardware engineers

[Karlos]

http://www.zachtronicsindustries.com/kohctpyktop/kohctpyktop.htm

This is great fun. Unfortunately for me, I'm stuck on the dual set-reset latch. I can't get the verification past 95%, so it fails. I'm using a dual NOR based design for each latch to minimise the number of gates (as gate delay is a factor), but my design still sucks as Q0 and Q1 basically oscillate until the system is initialised with an input. After that, the system works but there is up to a 2 gate delay in responding to the set or reset.

[X-ray]

If only I knew something more than 15% of diddly to the power of -128, I would enjoy that game.
Sadly I can only follow the advice below:
 

ACHTUNG! ALLES TURISTEN UND NONTEKNISCHEN LOOKENPEEPERS! DAS KOMPUTERMASCHINE IST NICHT FÜR DER GEFINGERPOKEN UND MITTENGRABEN! ODERWISE IST EASY TO SCHNAPPEN DER SPRINGENWERK, BLOWENFUSEN UND POPPENCORKEN MIT SPITZENSPARKSEN. IST NICHT FÜR GEWERKEN BEI DUMMKOPFEN. DER RUBBERNECKEN SIGHTSEEREN KEEPEN DAS COTTONPICKEN HÄNDER IN DAS POCKETS MUSS. ZO RELAXEN UND WATSCHEN DER BLINKENLICHTEN

[Karlos]

Try watching the tutorial in the help section, it'll make things a lot clearer.

In your chip, you have one silicon layer and one metal layer. There are 2 types of silicon and either kind (red for N type, yellow for P type) can act as a conductor. You only get a gate where you put one type of silicon on top of another.

You can't put 2 metal traces over the same square, nor can you put two types of silicon through the same square except where making a gate.

The only way to get two independent conductors through a square is to make one out of silicon and the other out of metal. In order to connect metal to silicon, you have to put a via point (indicated by the small circle).

The game also simulates gate delay, which becomes essential later on when you have to create delay lines and oscillators. However, if any of your designs has too much gate delay where it isn't wanted, it will fail the verification stage. meaning it is back to the drawing board.


Anyway I solved this last one I was stuck on by throwing away the idea of creating a dual NOR (which has several gates per NOR unit) based latch when I realised I could get away with just 2 gates with one feedback arranged like so:

Code: [Select]


 VCC  +--------+
  |   |        |
  +--NPN--PNP--+
      |    |   |
      S    R   Q


So simple, yet it gives the required behaviour with not more than one gate delay when setting or resetting.

[Karlos]

I dare say the FPGA wizards here will breeze through this game

[bloodline]

If only I knew something more than 15% of diddly to the power of -128, I would enjoy that game.
Sadly I can only follow the advice below:
 

ACHTUNG! ALLES TURISTEN UND NONTEKNISCHEN LOOKENPEEPERS! DAS KOMPUTERMASCHINE IST NICHT FÜR DER GEFINGERPOKEN UND MITTENGRABEN! ODERWISE IST EASY TO SCHNAPPEN DER SPRINGENWERK, BLOWENFUSEN UND POPPENCORKEN MIT SPITZENSPARKSEN. IST NICHT FÜR GEWERKEN BEI DUMMKOPFEN. DER RUBBERNECKEN SIGHTSEEREN KEEPEN DAS COTTONPICKEN HÄNDER IN DAS POCKETS MUSS. ZO RELAXEN UND WATSCHEN DER BLINKENLICHTEN

That is Very funny!!!

[bloodline]

http://www.zachtronicsindustries.com/kohctpyktop/kohctpyktop.htm

This is great fun. Unfortunately for me, I'm stuck on the dual set-reset latch. I can't get the verification past 95%, so it fails. I'm using a dual NOR based design for each latch to minimise the number of gates (as gate delay is a factor), but my design still sucks as Q0 and Q1 basically oscillate until the system is initialised with an input. After that, the system works but there is up to a 2 gate delay in responding to the set or reset.

I say, use a microcontroler to sample the inputs and then generate the correct outputs... What!? I'm a software guy...

[Karlos]

I say, use a microcontroler to sample the inputs and then generate the correct outputs... What!? I'm a software guy...

LOL. Oh well, anyway I got past that one. Now it's the bloody toggle latch that I'm finding a problem. Especially since the timing is tighter on this one.

[Oliver]

Just remember this stuff can't be synthesized as is. Its a good game, just the same. Logic, thought, design, re-use, and patterns all here.

Karlos, you may like to look at JK flip flops. They use an additional gate at each of the R,S inputs to avoid a race state.

I had a quick look at this yesterday. It seems that if transistor is not pulling high, then the output is considered low, rather than just open. At first, I was looking to use polycrystal, ground connections, and CMOS. I had wondered if the substrate was grounded, and if there was a via, with no metal layer, then it would be considered to be a ground connection.

I think it is a great simplification, though. It's fine for a game.

Anyone tried using PN junction diode logic? It can do very simple gates. Not much use for most things.

[Karlos]

Hi Oliver,

I've actually advanced past the latches, and got the set/reset latch down to a minimal number of junctions. The toggle latch was trickier as I based it on the same design, but to "debounce" it, it required a rising edge detection, but that's actually doable with a PNP junction that connects it's own output to it's base, giving a 1 gate delay duration high output whenever the input is high.

You get to build an 8-bit SRAM later, complete with a 3-bit address bus and read/write selector. I'm not quite up to that yet.

[Oliver]

Damn it, you're going to get me hooked on a game again. Hasn't happened for years.

[Karlos]

Damn it, you're going to get me hooked on a game again. Hasn't happened for years.

Yeah, I have wasted a few lunch breaks on it so far