Amiga - a 16bit or 32bit machine?

[ejstans]

The falcon used a 16-bit databus for the CPU. As I said, the 68020 (and 030) are perfectly happy running on narrow data buses. Only the number of cycles required to transfer 32-bit words is affected. You can run a 68020 on an 8-bit databus if you really want.

Hence the reason for preferring GPR width over concerns like buses and memory organisation.

My GPU has a 448-bit bus, I wouldn't call it a 448-bit machine

Gosh, what a silly thing to do, to needlessly starve a CPU on memory bandwidth! I doubt the 68030 was very happy with that arrangement!

Anyway, what possible use is it to dub a machine this-or-that many bits? By itself, such a number is completely useless. Remember the CD32. What a laff compared with Saturn or Playstation in the 32-bit console battle...

Hmmm, the Playstation, now that was a beautiful machine :cool:

[bloodline]

Not necessarily:
- Z80
- 68008 (!)
- 68000
- 8088
- Pentium (32 bit registers vs. 64 bit bus)
- ...

Well... obviously apart from all the CPU's that don't... :lol:

Win   +1

[bloodline]

A 16-bit address bus would be more of a problem. It would limit you to 64K address space. I'm not sure if the 680x0 is capable of running on a "narrow" address bus in the same way it does a data bus.

Yup, the Falcon suffered with a 16bit Data bus. The address bus can't be "multicycled" like the data bus.

[Karlos]

Well... obviously apart from all the CPU's that don't... :lol:

Win   +1

The Z80 had an 8-bit data bus and 8-bit general purpose registers. Strictly speaking BC, DE and HL were not general purpose registers but register pairings of more general purpose 8-bit ones.

Although, given the the machine belongs in the age of the "accumulator", you might as well pick the A reg only and not even consider the rest :lol:

[Karlos]

Yup, the Falcon suffered with a 16bit Data bus. The address bus can't be "multicycled" like the data bus.

Amigaski would have loved it though. Half of the reason for picking the 16-bit wide bus was to simplify maintaining hardware compatibility with bits they'd inherited from the ST. You know, rather than actually make best use of the new hardware they were engineering into it.

[ejstans]

oh noooo... not this old hat rechewed once again.

the 68000 was designed as a full 32bit cpu, only cost restriction caused external busses to be restricted to 16 (or late 24) bits. Study the cpu design docs as I did in 1991 for my university project.

end of story - move on

Tom UK

Well, that's not exactly how I remember it. It clearly wasn't designed as a full-fledged 32-bit cpu since important internal structures are only 16-bit.

It was realized that 16-bits did not provide enough address space, and rather than choosing some page-mode or other kludge they went all 32-bit on the address space. Only the lower 24 bits were routed to external pins as a means to keep pin count down and 16 MiB ought to be enough for everybody!

In order to avoid the mess with different sized address and data registers, the data registers too became 32-bit wide. The external data bus was only 16-bits though, probably to keep pin count down, but also maybe because 16-bit ops were thought of as the primary mode of operation and the slower 32-bit ops were only icing on the cake sort of speak...

[Karlos]

Whilst the ALU is 16 bits, I think there was a lot more to making a 32-bit register/instruction set model than "icing". Making the internal register model 32-bits wide was a mark of serious forward planning. Compare the 68000 to the 8086 design. After all, they'd gone for a separate data and address register model, they could easily have made d0-d7 16-bits wide and a0-a7 24-bits. It would have been cheaper and quicker to market.

[warpdesign]

Not really, no. The FM Towns Marty contained a 386SX, the SX variant of the 386 had a 16 bit databus, like the 68000.

Indeed. And the 68EC020 found inside the CD32 only has a 24bit address-bus and can't allocate more than 16Mb RAM... Get it isn't 32bit either So where does it leave us ?

[bloodline]

Well, that's not exactly how I remember it. It clearly wasn't designed as a full-fledged 32-bit cpu since important internal structures are only 16-bit.

It was realized that 16-bits did not provide enough address space, and rather than choosing some page-mode or other kludge they went all 32-bit on the address space. Only the lower 24 bits were routed to external pins as a means to keep pin count down and 16 MiB ought to be enough for everybody!

In order to avoid the mess with different sized address and data registers, the data registers too became 32-bit wide. The external data bus was only 16-bits though, probably to keep pin count down, but also maybe because 16-bit ops were thought of as the primary mode of operation and the slower 32-bit ops were only icing on the cake sort of speak...

The 68000 was designed to be comparable to the minicomputers of the time, like the PDP and the VAX... thus it's similarity to their architecture, including a 32bit data/address  model.

[Karlos]

So far, so many versions. All this thread has demonstrated to me is that the compiler vendors are the only ones with a clear definition of the "bitness" of an architecture

[Trev]

Interesting goody for Karlos: http://www.theregister.co.uk/2009/06/23/super_micro_gpu_node/

[the_leander]

So far, so many versions. All this thread has demonstrated to me is that the compiler vendors are the only ones with a clear definition of the "bitness" of an architecture

I know that some Amiga magazines sold advertising space to retailers who were selling the A3000 (with a graphics card) as a "24 bit" computer... Which was interesting.

[ElPolloDiabl]

From Wiki:

The Motorola 68000 is a 16/32-bit [1] CISC microprocessor core designed and marketed by Freescale Semiconductor (formerly Motorola Semiconductor Products Sector). Introduced in 1979 with HMOS technology as the first member of the successful 32-bit m68k family of microprocessors. It is generally software forward compatible with the rest of the line despite being limited to a 16-bit wide external bus. After three decades in production, the 68000 architecture is still in use.

It is 16/32-bit. In other words both. A hybrid more or less. The PPC is pure 32-bit.
The x86 is also a hybrid, so hybrids seem to be the norm.

[sim085]

The x86 is also a hybrid, so hybrids seem to be the norm.

Why is the x86 a hybrid? isn't it 32bit as well?

edit: ok I understand (read wiki article).

[Hammer]

Why is the x86 a hybrid? isn't it 32bit as well?

edit: ok I understand (read wiki article).

From wiki

All internal registers as well as internal and external data buses were 16 bits wide, firmly establishing the "16-bit microprocessor" identity of the 8086. A 20-bit external address bus gave an 1 MB (segmented) physical address space (220 = 1,048,576). The data bus was multiplexed with the address bus in order to fit a standard 40-pin dual in-line package. 16-bit I/O addresses meant 64 KB of separate I/O space (216 = 65,536). The maximum linear address space were limited to 64 KB, simply because internal registers were only 16 bits wide. Programming over 64 KB boundaries involved adjusting segment registers (see below) and were therefore fairly awkward (and remained so until the 80386).

Latest X86 supports X86-64 (aka X64, AMD64, Intel64, EMT64) ISA i.e. X86's 64bit ISA.

[Karlos]

From Wiki:

It is 16/32-bit. In other words both. A hybrid more or less. The PPC is pure 32-bit.
The x86 is also a hybrid, so hybrids seem to be the norm.

It's only a hybrid if you regard the physical bus into the outside world as important in the definition. That can vary even on the same processor. As I said previously, you can run a full 68020 on an 8-bit databus if you need to interface only with 8-bit peripherals.

The GPR definition is the best definition, since it overlooks all these considerations and focuses on the capability of the machine. If it has 32-bit general purpose registers that support the regular gamut of operations for 32-bit datatypes, then the machine is best described as 32-bit. The 68000 still falls into this category, even though it was slower at all 32-bit operations (using a 16-bit ALU and internal bus).