Cloanto's plans mentioned in Business Week OnLine

[Hammer]

Michele Battilana's Cloanto was mentioned in mainstream Business Week OnLine on February 26, 2004. It made reference for releasing a 'new' 64-bit software for the new Microsoft OS (i.e. "Windows XP 64-Bit Edition for 64-Bit Extended Systems").


Business Week Online Article

[samo79]

Good news, but the correct name is Michele, is italian !

[SHADES]

Not a very well researched nor written article.

16 bit systems could address more than 1 MB of ram. 64 bit CPU's like AMD have just released doesn't mean that you need to change your software or hardware.
Even if your OS utilized the 64 bit functions of the AMD chips, they were designed to be backward compatible and still run 32 bit code etc. It's a very clever thing to have done. AMD keep the huge base of 32 bit hw/sfwre and also give you the ability to do some 64 bit needs. IE you can still run your windows XP 32 bit or whatever it is you run on the AMD 64/32 bit chip that you already run on a 32/32 bit chip. why would corperations/hospitals need or have to upgrade their hw.
Ahh well.

Now for off topic.

Hurry up OS4

[Cass]

Forza Michele!!! :-) :pint:
Glad to see that AMiGA developers get the media's attention.
________
Motor Manufacturing Kentucky

[Hammer]

16 bit systems could address more than 1 MB of ram

Note that a true "16bit" processor (16bit address space) can only access 2^16 worth memory i.e. MC68000 is hybrid processor.

why would corperations/hospitals need or have to upgrade their hw.

For lowering the cost of HW which runs large MIS/Relational Database systems that exceeds 2^32(~4GB) memory i.e. 8GB of memory. AMD64 brings the 64bit processor market closer to the commodity X86-32 market.

[pixie]

I bought this months issue of Computers arts, and it had many references to Amiga, from a designer who *still* uses is Amiga for pixel perfect drawing (through PPaint), to how the new Aura (I think it's called Mirage)is heavely influenciated from DPaint and how Lightwave also evolved from Amiga...

[DanDude]

The Amiga will never die!!!
:-)

[SHADES]

@ Hammer
>>Note that a true "16bit" processor (16bit address space) can only access 2^16 worth memory i.e. MC68000 is hybrid processor.

Ok, fair enough I wasn't specific enough.
It all depends on the memory addressing ability.
IE. You can have an 8 bit CPU with a 14 bit memory Addres bus.
In 1974, Intel released the 8080 which was also an 8-bit microprocessor, but was built from nearly twice as many transistors as the 8008. It had a 16-bit address bus resulting in benchmarks of up to 1 million instructions per second.

The 16-bit address bus of the 8080 allowed it to access 64kB of memory. The first personal computers using this CPU usually had far less memory than the address bus limited them to.

So the article is still wrong. 1MB memory would result in the need to utilize a 20 bit address pathway like in the 8086 line of Intel CPUs had.
These CPU's were 16 bit internal but could access up to 1MB of data using the 20bit address pathway.

OR
Intel released a variant of the 8086 called the 8088. While still running at the same clockspeed and with the same capacity for memory addressing, IE a 20 bit memory address bus, this processor had only an 8-bit data bus. At that time, 8 bit architecture was prevalent, while 16 bit was not.
That's an 8 bit CPU with access to 1MB of memory.

>>For lowering the cost of HW which runs large MIS/Relational Database systems that exceeds 2^32(~4GB) memory i.e. 8GB of memory. AMD64 brings the 64bit processor market closer to the commodity X86-32 market.

Good point. I read the article as thought they would have to spend big in replacing all their HW and SW to run on the newer AMD 32/64 hardware which clearly isn't the case. The new platform will still run 32 bit software and the hardware that plugs in on standard PCI wouldn't change. PCI is already 64 bit in servers anyway.

Either way, the article was not reasearched well and wasn't writen with good examples to back up statements. Which is why I guess I came up with the answers I got.

[Aegis]

how the new Aura (I think it's called Mirage)is heavely influenciated from DPaint

Actually, Mirage (which rocks by the way) is the latest version of the Amiga's very own TVPaint - it was ported to the PC and had timeline based animation added to it as "TVPaint Animation" before NewTek sold it for a while under the name "Aura" (it's still included with the PC Video Toaster). The stand alone is now called Mirage and is distributed for the PC and Mac by Bauhaus Software (www.bauhaussoftware.com) If you use a PC or Mac and are a fan of DPaint or TVPaint you owe it to yourself to check it out...

[Hammer]

@SHADES

In relation to Intel's 8080, it has seven 8bit registers which can combine to form three 16bit registers (recalling).

Intel 8086 has four 16bit general registers but can be treated as eight 8bit general registers. The memory model in this CPU is defined in some circles as "brain damaged".

Note that; there is the PAE segmentation memory model in +P6 generation processors i.e. X86-32 can physically address up to 2^36bit of memory(via PAE) but it is divided into 2^32 segmented pages(recalling). Using this PAE extended mode can slow down the overall performance, thus the need for AMD64.

[Hammer]

That's an 8 bit CPU with access to 1MB of memory

Intel 8088 was a 16bit CPU with 8bit wide i/o data bus i.e. like MC68008. The "bit’ness" usually refers to how the CPU treats its internal data sets.

[SHADES]

@Hammer
True, it normaly does, however, CPUs are described as having certain data paths. This refers to how many bits of information can travel in parallel at one time.

I was commenting on the article misrepresenting this. It is not 16 bit that addresses 1MB of memory at all.

For example, a 16-bit data path is a 16 wire path on which 16 bits of information can travel at any time.
This results in roughly 2 bytes of information processed at a time or 2 x 8 bits = 16 wires or even 2x2 bytes because 1 byte = 8 bits.
Therefore, such a CPU is said to be a 16-bit CPU. Today's CPU's can handle much more traffic mainly because they are 32 bit or 64.

However the address bus is different than the above data bus.
The address bus is the wire path that carries addressing information that says where in the computer's memory to look for certain data.
Each wire can carry one bit of information.

Since computers think in binary (0's and 1's), a 2-bit address bus would provide four addresses (00, 01, 10, 11). A 3-bit bus would provide 8 addresses, and so on. The point of all this is that the address bus built into the CPU dictates how much memory the computer can have.

A 286 has a 24-bit address bus, thus providing 16,777,216 addresses. This means the 286 CPU can only address 16 MB of memory. The 386 and 486 both have 32-bit address buses which provide 4,294,967,296 addresses. These processors can address 4,096 MB of memory, even though no motherboards have enough slots to hold this much memory.
 
SO if we want to find out how much addressing we need for 1 MB of memory, it's quite simple really

2^20 = 1048576 bits

So if we go by your train of thought, being the internal path/width of memory addressing, the 8088 is actually a 20 bit CPU Providing we are still talking in bits of information that can be accessed here.

[Hammer]

So if we go by your train of thought, being the internal path/width of memory addressing, the 8088 is actually a 20 bit CPU Providing we are still talking in bits of information that can be accessed here

Note that it’s pointers(important for the "bit'ness") wouldn’t be at 20bits.

[Hammer]

>8088 is actually a 20 bit CPU

It’s more complex than that. To specify an
address you use a 16 bit base register and a 16 bit offset to form a 20 bit physical address (recalling the hack). Notice the use of two 16bit instructions. To access more than 64KB of memory, this hack must be use i.e. some commentaries associated this to "brain damage".

To compound the memory restrictions; the original IBM PC can be expanded to 256K (i.e. maximum memory using IBM parts at that time(1)).

Usually, "Bit’ness" refers to GPRs and Pointers.(simplifying). Note that the current X86-32 can ready handle 64bit data sets(e.g. 3DNow, SSE, AMD32's EV6 FSB, internal data path).

Reference
1. http://en.wikipedia.org/wiki/IBM_PC

[SHADES]

@Hammer
>>To specify an
address you use a 16 bit base register and a 16 bit offset to form a 20 bit physical address (recalling the hack)


Sort of. You want to be specific then we have to get specific.
It's called a bit shift. 8088 do what we call RMA Real Mode Addressing.
In real mode, each segment register (which is 16 bits in length) is internaly named whit a 0h on its rightmost end shifting it (the segment) left by 4 bits.
This segment and it's ofset are then added to form a 20 bit memory address.
This would limit CPUs to 1MB of memory space, even if the CPU was a 80486 CPU!

This is most clearly NOT nor is it reffered to be a 16 bit cpu.

80286 and later are further extended with their memory addressing capabilities by changing the function the CPU uses to convert a logical address to the linear address.
They commonly use what is known as a lookup table to compute the physical address.
This is also commonly know as Protected Mode Memory Addressing.

Basicly a segment value is used as an index into an array. A description table or look up table.

The contents of the selected array provides the starting address for the segment and then the cpu adds this value to the offset to obtain the physical address.

Anyway, all of this is irrelevent. I'm not dissagreeing with your above statement, but your not addressing the original argument.
The point is, that the article in question here stated that 16 bit processors accessed 1 MB of memory, which is not really correct. Even your own statements above confirm this. A true 16 bit CPU using the constraignts of 16 bit memory adressing would be far more limited than the 1MB constraint.

Here is a little intro into the memory addressing teqniques and their labled address widths etc..

http://courses.ece.uiuc.edu/ece291/lecture%5CSpring2004%5CLecture2.pdf