Announcement concerning the Genesi/Phoenix collaboration

[KennyR]

This is VERY good news for Amiga Inc. and Hyperion since one looser (Bill Buck) joins forces with another looser (David Greene).

It's loser, not looser!
And, uh, it's not like me to step in for Genesi, but...

I know some people would have something against Bill Buck out of anger about anti-AInc/A1/OS4 posts in the past (or just out of blind prejudice) but how can you even know David Greene?

Anyway, it's not so good for AInc as you think. Like it or not it's a very good alliance for Genesi, which is more than can be said for AInc's very foolish alliances when building the DE and later with the Evil Gatesian Empire, who eat small companies for breakfast and spit out the bones.

[Paul_Gadd]

As long as Buck and friends actually release products then that is all what matters.

[downix]

That's possible. Unless they have someway to emulate AGP on the PCI bus? The AGP signal set is a subset of the PCI Bus. After a discussion I had with a chap on the AmigaOne mailing list, it seems the internals of an AGP device have additional registers (GART) and they lack a few features of PCI.

Most of the difference between AGP and PCI is inside the chip, not in the bus itself.  There are several techniques to bridge an AGP bus onto a PCI bus out there.  I would point out that the Marvell has PCI-X, which rivals AGP 8x in speed.  This means that some bandwidth can be lost in the translation process and still get top-speed AGP functionality.  Even a standard PCI 64-bot 66-Mhz bus can be bridged to deliver AGP 2x speed to a peripheral card.  The card doesn't *care* how the northbridge actually handles it, so long as it gets the bandwidth needed.

I would note, Genesi has several talented VHDL/Verilog coders among their staff.

[MarkTime]

just read above, so editing my post...

of course the card doesn't care, but what I don't understand why it is cheaper or more effective to build this bridge solution than to just build a northbridge that does what you want.

frankly this does go into the realm of internal developer decisions, that I don't really care about.
But I did find it interesting that Genesi can announce, DDR support, they can announce the CPU support,
they can even tell us the brand name on the northbridge, but they cannot tell us if it will support AGP or not.

So far anyway, the only thing I got on ANN was a supporter saying that was an internal engineering question that Amigans wouldn't care about....excuse me, don't care about the accelerated graphics port?  They can name every chip in their machine.....

sigh

[amigamad]

pci cards are old and very expensive we are meant to be going forward not ten years back


ill stick to my amigaone. :-)  :-)

[strobe]

@downix

Well hopefully they will aim higher than AGP 2x

[downix]

of course the card doesn't care, but what I don't understand why it is cheaper or more effective to build this bridge solution than to just build a northbridge that does what you want.

The logic needed is far cheaper.  An AGP bridge to PCI uses between 2000 and 3000 gates, that's a $2 programmable array.  A whole northbridge can run upwards of 400,000 gates for a simple one, over a million for one that can match the Marvell in performance.  A 1 million gate array that runs at the speed needed is $300 or more.

As for the final speed, the speed won't go down any from the bridge, but nobody will commit to the final speed until we've finished testing it.  Genesi does not like to break promices, and while we are very sure that we can get one speed out, we're making damned well sure first before advertising it.

[MarkTime]

@downix

Thanks, well that 'splains it.
Quite frankly I was worried that a pci solution would be the end result.

pci solutions do exist...both in server rooms, and in the low end consumer market.  Many an inexpesnive machine at least lacks a agp port (even if some have integrated agp).

It will be good news indeed if the peg2 finishes soon.
I have confidence they will have an OS to run on it, so they have one of the major issues solved already.

[AmiGR]

That's why AGP ****WILL**** be on the Peg 2.

[Ryu]

hmmm someone remind me, whats morphzone.org for?

[MiniBobF]

Most of the difference between AGP and PCI is inside the chip, not in the bus itself. There are several techniques to bridge an AGP bus onto a PCI bus out there. I would point out that the Marvell has PCI-X, which rivals AGP 8x in speed. This means that some bandwidth can be lost in the translation process and still get top-speed AGP functionality. Even a standard PCI 64-bot 66-Mhz bus can be bridged to deliver AGP 2x speed to a peripheral card. The card doesn't *care* how the northbridge actually handles it, so long as it gets the bandwidth needed.

Yeah, but how many PCI-X graphics cards do you see available on the market??? They're either AGP or 32-bit 33MHz PCI.

Neil Thomas, AKA MiniBobF

[downix]

Yeah, but how many PCI-X graphics cards do you see available on the market???

A few, but why do you ask as there won't be a PCI-X slot on the motherboard, just the PCI's and an AGP slot.

[Hammer]

Which PCI-X speed grade does this Marvel chipset supports?

Refer to http://www.pcisig.com/specifications/pcix_20

PCI-X 2.0 is a new, higher speed version of the conventional PCI standard, which supported signaling speeds up to 533 megatransfers per second (MTS). Revision 1.0 of the PCI-X specification defined PCI-X 66 and PCI-X 133 devices that transferred data up to 133 MTS, or over 1Gbyte per second for a 64-bit device. The present revision adds two new speed grades: PCI-X 266 and PCI-X 533, offering up to 4.3 gigabytes per second of bandwidth, 32 times faster than the first generation of PCI. Another major feature of the PCI-X 2.0 specification is enhanced system reliability. ECC support has been added both for the header and payload, providing automatic single-bit error recovery and double-bit error detection. These new standards keep pace with upcoming advances in high-bandwidth business-critical applications such as Fibre Channel, RAID, networking, InfiniBand™ Architecture, SCSI, and iSCSI.

[MiniBobF]

PCI-X 2.0 is a new, higher speed version of the conventional PCI standard, which supported signaling speeds up to 533 megatransfers per second (MTS). Revision 1.0 of the PCI-X specification defined PCI-X 66 and PCI-X 133 devices that transferred data up to 133 MTS, or over 1Gbyte per second for a 64-bit device. The present revision adds two new speed grades: PCI-X 266 and PCI-X 533, offering up to 4.3 gigabytes per second of bandwidth, 32 times faster than the first generation of PCI. Another major feature of the PCI-X 2.0 specification is enhanced system reliability. ECC support has been added both for the header and payload, providing automatic single-bit error recovery and double-bit error detection. These new standards keep pace with upcoming advances in high-bandwidth business-critical applications such as Fibre Channel, RAID, networking, InfiniBand™ Architecture, SCSI, and iSCSI.

I'm not sure I understand the question, so please forgive me if the answer isn't relevent!!

The clock for PCI-X varies depending on how many devices are on the bus.

1 device (point to point) = 133MHz
2/3 devices = 100MHz
4 or more = 66MHz

If you plug a non-PCI device in, you'll degrade the bus to 33MHz only (or 66MHz if the non-PCI device happens to be a PCI-66 Part).

Neil Thomas, AKA MiniBobF

[Hammer]

Based on the quote above, my question was just about which PCI-X version does the Marvell chipset supports.

[Hattig]

I would point out that the Marvell has PCI-X, which rivals AGP 8x in speed.

PCI-X at 133MHz and 64-bits is AGP 4x in speed. No great difference in the real world ... but ...

AGP is 32-bit, with 2 or 4 bits sent per clock (66MHz for 2x, 4x and 133MHz for 8x IIRC). When you put an AGP device on a PCI bus, you can only send one bit per clock. So you would be limited to AGP2x speed even with an AGP8x device ... unless you made a bridging chip, or more realistically, used an as-yet-unannounced Marvell northbridge that implements AGP instead of PCI-X.