"As the 68040.library requires an MMU to map address space, the fix described above will not work on systems with a MC68EC040. Because burst mode on the 68040 is activated along with the cache, there is no way to prevent a 68EC040-equipped Amiga from doing full line bursts when accessing cachable address space. This means a 68EC040 cannot prevent the excessive reads and writes when reading non-cachable ZorroIII devices that reside in cachable address space. A 68EC040-equipped Amiga will experience a significant decrease in performance when accessing non-cachable Zorro III devices. For this reason we cannot recommend that anyone use a 68EC040 (or any future 68000 series CPU that has no MMU) as the CPU on a Zorro III bus system."
All the EC processors have access control registers for controlling the cache. You don't need an MMU, although as you can only use the high 8 bits of the address and you need to make the custom chip registers non cachable as well you would have to be careful with where you put your cachable and non cachable boards to achieve the best performance.
The following is also true of a 68ec040
"On an Amiga with a 68040, Exec uses one of these registers to map the low
24-bits of the Amiga's address space (the Zorro II range,
$00000000-$00FFFFFFFF) as non-cachable and serialized1 .
The Amiga uses the second register to map the remaining memory
($01000000-$FFFFFFFF) as cachable and non-serialized. Because of its
mapping, any RAM in this region will yield considerably higher
performance than RAM in Zorro II space. Unfortunately, this mapping
can cause problems for a Zorro III device that is not RAM."
By changing the ranges that are cached/non cached and making expansion.library put boards in the correct place depending on whether they are ram or not you would avoid the problem. I don't know why they didn't do that. Especially at a time when dedicating nearly 4gb of address space to ram was insane.
