As close as I understand that side of it, I'm a code monkey so whilst that side of it is accessible and I've helped make some changes I don't have the experience of extrapolating that to the VHDL.
All of the interfacing with it from software is done pretty closely to hardware. I.e. registers get set - like lighting values, triangle setup are all pushed into their own registers etc, on the next "tick" the hardware takes them into the pipeline and passes them through each stage.
In the simulator things are quite different to the hardware, there's no per-stage tick for the pipeline, its just done as a series of serial functions like you would in a software rasteriser. This makes it easier for software guys like me to contribute to the graphics development with the occasional worry about using sqrtf() and pow() etc :-D
EDIT:
hardware registers, clocks, pipelines, RAM buffers etc. ?
Or (more likely) is it just a SW renderer experimenting with little more than algorithms? (perhaps ones which may or may not be possible to easily turned into hardware)
Its a bit of both, abstracted interface using registers and a tick to start off each update of the pipeline. Some ram buffer simulation and a basic pipeline, but the pipeline behaves more like a software renderer than a true simulation should I'd bet.
It's sort of a tradeoff, an attempt to get the software API and algorithms done in a hardware implementation "friendly" manner. Then a period of culling non-hardware decisions. Rinse n' repeat.
Andy
