@MikeJ
Will the cores be released as opensource when they are ready?
In general yes, I am a very keen on everything being open.
If there are any IP issues (I can only think of two, one being part of the ST chip set and the other part of my memory controller) I'll release that sub-module as obfuscated (scrambled) VHDL. In this way you can still recompile the chip and add new features to 99% of the code.
I intend all the code to be fully open from day one if possible, so I hope this will not be necessary.
The ARM code will also be available as are the schematics and a developer wrapper file for the FPGA which drives the various interfaces and has a standard interface to the different cores.
Best,
Mike