Arcade game "1943 : the battle of midway" running on an FPGA!

[FrenchShark]

Hello,

It is a little bit OT but, it can be interesting for Minimig owners.
I have ported the coin-op game from Capcom to an FPGA.
Check this little video:
http://www.youtube.com/watch?v=9UuDf9zZqCg

The game fits in 3500 LEs (I did not write the sound part yet).
It is displayed on a VGA screen at 1280x1024, 60Hz.
The internal architecture is built on 16-bit bus running at 24 MHz (384 clocks per scanline, 1048 lines per frame) with a 8-channel DMA scheduler :
- the main Z80
- the audio Z80 (not used yet)
- the scroll #1 tilemap
- the scroll #2 tilemap
- the scroll #1 graphics
- the scroll #2 graphics
- the sprite graphics
- the character graphics
All the game ROMs (864KB) are stored in an external SSRAM and are accessed through DMA.

If the Minimig HW is fitted with 10ns SRAM, it is possible to run this game.

Regards,

Frederic

[Darrin]

Nice work.  So, is the standard aCube Minimig fitted with 10ns SRAM?

I must admit to liking 1943.  The Amiga version of 1943 runs well, but a pure arcade version would be very nice.

[FrenchShark]

Darrin wrote:
Nice work.  So, is the standard aCube Minimig fitted with 10ns SRAM?

Unfortunately no, it has 55ns SRAM.
I think it may be possible to optimize the DMAs to make them run on a 16 or 12 MHz bus :
One cycle out of 4 is given to the main Z80 and one cycle out of 8 to the audio Z80. But, these two Z80 use 8 bits out of the 16 bits read. With a simple caching of the second byte fetched, almost 50% of the Z80 fetch cycles can be saved.
The FPGA implementation can display 128 sprites per scanline, which will never happen (even the NeoGeo displays a maximum of 96 sprites per scanline). A lot of DMA slots are wasted here. I think I might be able to set the limit to 32 or 48 sprites.

I must admit to liking 1943.  The Amiga version of 1943 runs well, but a pure arcade version would be very nice.

Honestly, I was pretty disapointed by the Amiga version.

The FPGA version seems to be smoother than the arcade : there is no slow down when a lot of sprites are on the screen. This is because I made the main Z80 working at 24 MHz instead of 6 MHz. Just the instruction fetches are limited to 6 MHz. The animation is anyway synchronized with the VBLANK interrupt so the extra speedup on the Z80 does not turn the game into an implayable one.

Now, I am working on a scale2x algorithm to improve the graphics.

Regards,

Frederic

[jensl]

Frederic, do you have a partnummber from Digikey for 10ns ram that will fit into the minimig ?

Edit:
Could this sram working ?
IS64WV51216BLL-10CTLA3
http://www.issi.com/pdf/61-64WV51216.pdf

I will try this for you.
Do you think games with 68k and z80
are possible on the minimig ? Maybe the cps1 and cps2 games.

Jens

[whiteb]

Would the Minimig (in Amiga mode) benefit from faster ram over the Ram used already ?  And pin to pin compatibility ? compatibility ?

How is it going to affect the game, with the 68000 Hardwired on the board ?

[Illuwatar]

The only difference between IS64WV51216 and IS62WV51216 used in MiniMig is the numbering order of the address lines. Power, data and control lines are all in the same place.

[whiteb]

jensl wrote:
Frederic, do you have a partnummber from Digikey for 10ns ram that will fit into the minimig ?

From what i have seen, there ARE compatible 10ns Ram, but I don't like the order quantities from Digikey (Like, 1000)

Not spending $18,000 just because I want two of the {bleep}s.
At that rate, I would buy two pieces at $77 each from Farnell.

[whiteb]

Illuwatar wrote:
The only difference between IS64WV51216 and IS62WV51216 used in MiniMig is the numbering order of the address lines. Power, data and control lines are all in the same place.

So, then does that mean they are not compatible ?, because the  Address lines are ordered differently ? (I would have thought that it DOES matter), The FPGA would be calling Addresses on the wrong pins, Meaning that the FPGA core would need to be recompiled with the appropriate Address lines on the correct FPGA pins for the board layout.

[jensl]

This part should also work.
IS61WV51216BLL-10TLI and is orderable in 1 quantity for about 17$ from Digikey

Jens

[whiteb]

jensl wrote:
This part should also work.
IS61WV51216BLL-10TLI and is orderable in 1 quantity for about 17$ from Digikey

Jens

But the pins are different.

Look at the minimig 1.1 Schematics, compared to the PDF from Digikey.

An example, Pin 23 (A13, RAM_A14 on minimig) is A10 on the chip, the point I am making is that the FPGA would need recompiling to match the NEW address lines for the chips.  They may be Pin for pin compatible for +V or GND, and Data, but the Address pins are different.

On minimig's FPGA, RAM_A14 is on pin 64 of the FPGA, for the new chips, Pin 23 is A10, which on the FPGA is RAM_A11 (Pin 61).

 

[Illuwatar]

I don't think the address line order actually matters in this case. Yes - you will end up, reading a different memory cell compared to the correct RAM type, but you will always end up at the same cell. SRAM does not care about order as long as you are inside the address range.

But the price and availability is an other issue... :-(


Edit: IS61WV51216 and IS64WV51216 do have the same pin layout (they share the same data sheet too), so you have the address line renumbering issue in both. If there were sockets for 44-TSOPII, then this would be a simple issue to test (or if someone have some professional resoldering station that removes SMD without damaging the PCB).

[whiteb]

Illuwatar wrote:
 If there were sockets for 44-TSOPII, then this would be a simple issue to test (or if someone have some professional resoldering station that removes SMD without damaging the PCB).

I have taken these chips off Damaged boards before, but that was with a standard 20W soldering wand, I would not wish to push my luck.  The board was damaged any way, and i was moving the chips to a fresh new board, several pads DID move but again, board = damaged any way = Me not care.

For the record, this was a Minimig board that someone else messed up the FPGA soldering, so slowly I am moving the components over to the new board, and I am probably going to do the Clothes Iron trick to get the FPGA off.

http://uk.youtube.com/watch?v=976AIzyTyv8

[edit] hey where do you get this bloody stuff from ?
http://uk.youtube.com/watch?v=FTQqjggeklo&feature=related

[jensl]

Haha, nice trick with the flat-iron.
I use every day the hot air from Leister.
http://www.klappenbach.de/html/hot_jet_s.html

I will order some 10ns sram from digikey.

I will report the results next week.

Jens

[FrenchShark]

Illuwatar wrote:
I don't think the address line order actually matters in this case. Yes - you will end up, reading a different memory cell compared to the correct RAM type, but you will always end up at the same cell. SRAM does not care about order as long as you are inside the address range.

Illuwatar is completely right about address lines ordering.
Some SRAM manufacturer like Cypress just specifies A0 and A1 locations in their SSRAM datasheet (because of burst mode), the other address pins are just named "A".
The same remark is valid for the data lines (as long as you keep the data lines in the same byte group for x16 and x32 chips)

Regards,

Frederic

[FrenchShark]

jensl wrote:
Haha, nice trick with the flat-iron.
I use every day the hot air from Leister.
http://www.klappenbach.de/html/hot_jet_s.html

I will order some 10ns sram from digikey.

I will report the results next week.

You won't notice any speed improvement with Minimig.
The DMA scheduler has to be rewritten for that.
That would be a nice project : 57 MHz bus speed, 4 times the AGA speed...

Regards,

Frederic