FPGAARCADE minimig compatible board, comments?

[JimS]

mikej wrote:
that starts with "e"

How about "enabler"
or "emplementation" and claim the misspelling is a marketing thing. ;-)

[jkonstan]

Mike,

I did not see the termination resistor (@ 100 ohm depending upon the actual Zdiff of Mem_CLK_P & Mem_CLK_N) across the DDR diff pair of Mem_CLK_P & Mem_CLK_N. This termination resistor should be placed near U6, the DDR IC (TSOP66).

  :-)

[freqmax]

Ouch.. the impedance chores of DDR. Better stay with SDRAM
Guess we may have some reflections ..?

As for naming, it should make sense. And any words involved should be easy to say phoneticly. Or else people are most likely to call it something else very quick.

[jkonstan]

DDR takes a bit more simulation work than SDRAM; however, the memory bandwidth performance boost vs SDRAM is worth the effort if you have access to a SI simulation tool such as Hyperlynx.


 :-)

[jkonstan]

DDR pcb layout is more than just reflections & crosstalk.
DDR pcb has to be impedance controlled, and you have to have a range/window of trace length matching for different group of DDR I/O in order to meet timing requirements of DDR.
 :-)

[freqmax]

How feasable is to make a working pcb with only one DDR memory + one FPGA in close proximity without any non-free simulation tools?, or even without?

[mikej]

"I did not see the termination resistor (@ 100 ohm depending upon the actual Zdiff of Mem_CLK_P & Mem_CLK_N) across the DDR diff pair of Mem_CLK_P & Mem_CLK_N. This termination resistor should be placed near U6, the DDR IC (TSOP66)."

The memory clocks are complimentary signals, not differential so I have got two 51R to VTT placed after the memory. I would use a 100R between the P and N signals if I did not have a termination supply.

As the traces are quite short, and the board is pretty close to 50R on the signal layers, I think I could actually get away without the termination on the rest of the signals, certainly on the address lines. I have run it through Hyperlynx and the signals look ok, but they are better with the termination.

I think what will happen is I'll build a test board without the terminators and just a 100R across the clock nets and see how wide the margins are. A cost reduced board may follow later.
Cheers,
Mike.

[mikej]

"DDR pcb has to be impedance controlled, and you have to have a range/window of trace length matching for different group of DDR I/O in order to meet timing requirements of DDR."

I am matching all the DDR signals to the clock pair within 50ps. You can cheat a bit and fiddle things with the FPGA to an extent to put the clock in the correct phase with respect to the write data. Recovering the read data is a right pain.
/Mike

[jkonstan]

Mike,

Most DDR designs that I have worked on or have seen had used had a @ 100ohm termination resistor across the DDR_CLK+/DDR_CLK- nets even when there was a termination supply and resistors to VTT(1.25V). Micron does call the DDR_CLK+/DDR_CLK- nets a differential clock (See Micron Technical note TN-46-14: Hardware Tips for Point-to-Point System Design).
 
DDR is a little more flexible with respect to trace length mathcing.

Here are the generic DDR_SDRAM net rules that I typically use:
------------------------------------------------------------------------------------------
 1. The DDR net groups (databyte0, databyte1, and Address/control) should be within 100mils of each other in length.
 2. All DDR nets should be within 500mils of each other in length.
 3. The DDR_CLK+/- should be within 20mils of each other in length.
 4. The DDR_CLK+/- should have @ Zdiff=100ohms+/-10ohms.
 5. Target Impedance for DDR nets should be in range 40 to 50 ohms.
 6. The DDR Data nets & DQMx for DATABYTEx in relation to data Strobe DQSx should be within plus/minus 35 mils in length.

Cost reduced DDR termination (short trace lengths and only a couple DDR ICs) would would genrally consist of series termination on DDR nets, a @ 100ohm termination resistor across the DDR_CLK+/DDR_CLK- nets, and VREF (1.25V) generation via resistor divider (1K/1K) of 2.5V DDR supply with a small .01uf cap for each Vref pin for each DDR IC. In Cost reduced DDR termination scheme, the National LM2995 VTT (1.25V)termination supply can be eliminated along with all of the resistors to VTT.

As long as you run simulations in Hyperlynx, you will be fine.

 :-)

[mikej]

Good advice, thanks.
I have been working with DDR2 recently (I design ASICs which use DDR2 external memory). We made a few boards and experimented. We found that for short traces you can use no termination up to at least 600Mbit as long as you are point to point with no additional vias. Adding the series termination made things slightly worse actually, we think due to the via stubs.  

With the Spartan3 I haven't got the same control over the memory timing or drive strength/termination I get with Virtex5 or the ASICs, so I am being a bit more careful. I've put the termination resistors in the middle of the trace which works well in simulation. It also has the benefit I can remove them to test that configuration without any stubs.

I saw the Micron app note. As far as I can figure out the input buffers for the clocks are single ended, so in theory the traces should be 50R impedance and terminated to VTT. Most people do use a 100R across the clocks, but if there is any skew between the clocks the VTT termination would work better. In our designs with faster memories (RLDRAM and SRAM) we always use a resistor to VTT. I could save a resistor though .....

Cheers,
Mike.

[mikej]

ha ha, that should be complementary clocks not complimentary - although I quite like the idea of free clocks

I am discussing this 100R verses two 50R with some other people, looking around you see both. I am not sure at the moment which is "more correct" - they are probably both fine.
/Mike

[jkonstan]

Mike,

an extra set of 0402 or 0603 pcb pads & a resistor are very inexpensive; thus, I always include the pcb pads for a termination resistor across the DDR_CLK+/DDR_CLK- nets.

  :-)

[Methuselas]

Why not just call it Perfectly Obsolete Retro Nostalgia.

The way you guys are talking about it, it may as well be.


 :roll:  :crazy:  :lol:


[EDIT] - There's an ad with a bunch of guys sitting in front of a TV, all holding a joystick attached to this device box. I can see the tag-line now:

"When the wife's gone, it's time to break out the P.O.R.N.!"

[mikej]

"Why not just call it Perfectly Obsolete Retro Nostalgia."

mmm, actually that's not a bad idea

Updated layout pictures from the complete board at www.fpgaarcade.com
It's off to manufacture we go ....

Regards,
/Mike

Edit: Fixed link, thanks Chris.

[Darrin]

mikej wrote:

Updated layout pictures from the complete board at www.fpgaarcade.com. It's off to manufacture we go ....

Regards,
/Mike

Edit: clicking on the link doesn't seem to work, but then hitting reload does. Odd.

Excellent work/news Mike.

I hope you don't mind if we create a new section over on www.Minimig.net for your board.

Personally, I cant access the page at all from AOL.

[tonyyeb]

mikej wrote:

Edit: clicking on the link doesn't seem to work, but then hitting reload does. Odd.

You have a full stop at the end of the link.