Minimig released for real!

[alexh]

Yeah, right. Simple as that, I'll make the changes now :-P

"refresh_screen()" Heh, I love it!

Sorry, but you asked for that.

Concept wise, yes, if there is enough BLOCK RAM available in the FPGA then scan rate conversion is a possibility. Scrolling will suck but at least it will work. The PicassoIV's scandoubler has scan rate conversion.

I favour the 60Hz NTSC approach first. A change of crystal and an hour or two of modding and testing (less with feedback from top Amiga programmers, Dennis and Toni Wilen etc.) should get it working.

[freqmax]

No need to change crystal, just alter clock_dcm.v to output NTSC colour frequency.
I looked around on TFT specifications, seems 50 Hz is more doable than 100 Hz. As some of them actually supports 50 Hz. The upper limit seems to be 75 Hz for many screens. However I belive there are 100 Hz capable screens. And the onboard RAM could be used as frame buffer if the video output can't be scanned twice the normal rate.

[alexh]

freqmax wrote:
No need to change crystal, just alter clock_dcm.v to output NTSC colour frequency.

Give me the DCM values to produce an NTSC colour frequency from a 4.433619 MHz PAL crystal (which is what ships on a MiniMig)

[freqmax]

Frequency 3.575499 MHz with multiply=25 division=31
Ie 4.433619*(25/31)
If 0.001 MHz deviation works out alright.

[alexh]

How many DCM's are there in the XC3S400-4PQ208C? Four?

Can you cascade them?

MiniMig (NTSC) uses the following clocks:

3.579545 MHz
28.63636 MHz
7.15909  MHz
0.715909 MHz

http://www.amiga.org/forums/showthread.php?t=30550

I am not sure the DCM instantiated in MiniMig has all possible I/O. Making these clocks (within tolerance) may be possible.

http://www.xilinx.com/support/documentation/user_guides/ug331.pdf

I dont really have a working knowledge of these things.

[freqmax]

I think it's possible to cascade DCMs. And XC3S400 & XC3S500E both have 4x DCMs.

These clocks can be done without DCM (provided the 28MHz):
28.63636 MHz / 8 = 3.579545 MHz (colour clock)
28.63636 MHz.. (agnus)
28.63636 MHz / 2 = 7.15909 MHz (m68k cpu)
28.63636 MHz / 40 = 0.715909 MHz (E clk)

The key issue is timing, thus the colour coding schemes which another person mentioned is quite irrelevant as output is direct RGB.
I don't think the colour frequency crystal is needed at all actually. One could simple hookup to the MCU crystal and thus eliminate one crystal + associated passives.

I think a pure HDL solution is doable if the slight timing deviation is tolerable.