Assembled Minimig v1.1, larger FPGA (BGA-package)

[Belial6]

OK, maybe this is a stupid idea, but what about having the BGA FPGA put onto a daughter card, so that other revisions of the MiniMig could use the same FPGA without the BGA worries?  Are the electrical tolerances to tight for that? :crazy:

Of course I certainly don't want to discourage a run of fully factory assembled MiniMigs! :-D

[ThomasML]

Belial6 wrote:
OK, maybe this is a stupid idea, but what about having the BGA FPGA put onto a daughter card, so that other revisions of the MiniMig could use the same FPGA without the BGA worries?  Are the electrical tolerances to tight for that? :crazy:

I'm not going to put the FPGA on a sep. card, no, that would be to expensive, I'm afraid.

--
Thomas

[Belial6]

Is it only a cost issue, or is there a technical reason?

I do understand that cost matters, so I'm not trying to persuade you to change your mind.

[ThomasML]

Belial6 wrote:
Is it only a cost issue, or is there a technical reason?

I do understand that cost matters, so I'm not trying to persuade you to change your mind.

It's perfectly doable to stack FPGAs, and I'm looking at adding a set of connectors to be able to connect more FPGAs to the design by making daughter-cards with the right set of connectors.

But making such cards is on of the tasks that should be on the todo-list, rather than on the "to get it working in the first place"-list.

--
Thomas

[freqmax]

@Hans_:
Reflow oven:
* http://dlharmon.com/solder/smd.html
* http://www.seattlerobotics.org/encoder/200006/oven_art.htm
* http://www.elektor.com/magazines/2006/january/smd-reflow-soldering-oven.58007.lynkx  
* http://openhardware.net/Misc_Stuff/ToasterSMD/

Why is 68020+ needed for 24bit RGB?, dram speed have improved speed since Amiga
days, if that's the bottleneck.

Also many monitors have a hard time to make use of 24bit over analog transmission afaik. DVI or HDMI would proberbly be more suited for such high colour dynamic.

@Belial6:
How should the FPGAs cooperate?
Better to have one large FPGA. Only needs a rerun of Webpack P&R anyway. If the m68k is included in the source code anyway. Or to add/remove extra i/o capabilities.

[Hans_]

freqmax wrote:
@Hans_:
Why is 68020+ needed for 24bit RGB?, dram speed have improved speed since Amiga
days, if that's the bottleneck.

Not needed, but AGA is 32-bit and the 68000 has a 16-bit external bus.

Hans

[Belial6]

@freqmax:
I think there is some confusion.  In never suggested a second FPGA.  That was suggested by ThomasML.  I was just asking if there was a technical reason to have any FPGA soldered directly on the board.  It seems that it is only a cost issue.

My original thought was that since the BGA package of the larger, more powerful FPGAs is the biggest limiting factor on some of the enhancements some people are considering, maybe having a board with nothing but the FPGA and a connector would make sense.  This would allow larger more powerful FPGAs to be used in multiple designs, without every hardware revision having to be factory assembled.

ThomasML implied that this would be cost prohibitive.  Thus answering my question.  He also added that he is considering at a later date, working on a slot to add a second FPGA.  While this was not an answer to the question I was asking, it was interesting none the less.

[freqmax]

@Hans_:
Maybe I should ask like this, is it due memory bus speed or some other issue that a 32-bit bus is needed?

@Belial6:
Enterpoint have an assembled FPGA+32M SDram on a PGA socket header. This would allow FPGA upgrade at will. (cost 110E)

[Hans_]

freqmax wrote:
@Hans_:
Maybe I should ask like this, is it due memory bus speed or some other issue that a 32-bit bus is needed?

Basically all AGA software was designed for a machine with a 32-bit bus and a minimum 68EC020 processor running at ~28MHz. A 16-bit bus means half the memory bandwidth, and a slower processor will just make things worse. I'd expect most AGA games to fail to work properly on anything less than the basic A1200 specs.

Hans

[freqmax]

@Hans_:
The memory bandwidth of Minimig is artificially throttled (according to Dennis). So it should be possible to use the full bandwidth of the ram to feed the AGA graphics.

[adonay]

Ï want one.  :-D

[Hans_]

@freqmax

freqmax wrote:
@Hans_:
The memory bandwidth of Minimig is artificially throttled (according to Dennis). So it should be possible to use the full bandwidth of the ram to feed the AGA graphics.

It's the bandwidth between the CPU and the chipset that's the problem, not the chipset and memory. The timing of the CPU's bus is limited by the CPU. You could get the AGA chipset working, but performance would be substandard because the CPU is slow and it's memory bandwidth too limited.

Hans

[ThomasML]

freqmax wrote:
Yes.
Less vias => cleaner design => less emi etc..
And easier to track wires if the need arise.

This is how I'm suggesting that the layout will be:




Feel free to comment

--
Thomas

[jkonstan]

Did you rebuild the MiniMIG Xilinx ISE Project with the new Spartan3E part/BGA package to make sure that new pin out would route (i.e. is the resulting pinout from Xilinx ISE floor planner)?

Also, please see Xilinx Spartan3/3E APP notes on BGA 4/6layer PCB and on SSO (Simultaneous switched outputs).

http://www.xilinx.com/xlnx/xweb/xil_publications_display.jsp?iLanguageID=1&category=Publications/FPGA+Device+Families/Spartan-3E/Application+Notes
Check Xilinx XAPP689.pdf
Check Xilinx Xapp489.pdf

 :-)

[AJCopland]

lol well i can't comment on the technical side of it but it looks like all the main blocks I can identify are there. You'll have 10 user_io pins left. All 16 of the CPU address and data lines, likewise for the ram.

After that it all starts to look like a complicated game of scrabble :-D

Andy

[ThomasML]

jkonstan wrote:
Did you rebuild the MiniMIG Xilinx ISE Project with the new Spartan3E part/BGA package to make sure that new pin out would route (i.e. is the resulting pinout from Xilinx ISE floor planner)?

No, I'm pretty sure it'll route well, but I'm about to install ISE and compile it now.  Will let you know if there's any suggested changes from ISE.

The FPGA I've chosen has 1200k gates, tho, so it's a bit bigger than the one on the minimig today.  It's also large enough to fit a 68k inside the fpga.

Also, please see Xilinx Spartan3/3E APP notes on BGA 4/6layer PCB and on SSO (Simultaneous switched outputs).

http://www.xilinx.com/xlnx/xweb/xil_publications_display.jsp?iLanguageID=1&category=Publications/FPGA+Device+Families/Spartan-3E/Application+Notes
Check Xilinx XAPP689.pdf
Check Xilinx Xapp489.pdf

Yeah, I'll make sure to read those when I'm done with the schematics and starting on the pcb-layout.  I've been altering a few things more than once lately, as I've been talking to Dennis on email and getting a few ideas here and there :-)

--
Thomas