I thought a little more about my A600, my accelerator, and made my own mind about some things:
I hate SMC designs, they are not for hobbysts
I dislike ICs which are not DIL for the same reason
So what the hell was i doing with an A600 in the first place! I will try to find an A500 and continue work with it. It is so much easy to hack! Anyway as i mentioned before it is just a different micro layout, and Schoenfeld is about to sell his own, so i dont want to infringe any damage as little as it coul be, to his company!
I made up my mind: an A500 on-chip accelerator, will fit with no troubles many Amiga models as some of you have stated previously (A2000, A1000, A1500, etc).
I read about the Lucas accelerator and the Frances memory board. Too much interesting mental notes were taken in that process, and i eventually could draw some conclusions about my own project.
Even though, i need some help here!
68000 to 68030 interface:
As stated in the Lucas accelerator project, the idea is to make the 68030 resemble an 68000 at 7mhz to the amiga system bus. However, both microprocessor are not pin to pin compatible and have a few different control signals not to mention speed. So this is the actual challenge!
Differences to be solved:
1- Different clock rates
2- Data and Address signals
3- Bus length,/DTACK vs. /DSACK0 and /DSACK1
4- Byte addressability, /UDS and LDS vs. /DS
5- E clock generation at 1/10th of clock signal (0.7mhz)
The help i need is regarding item number 4. In the Lucas accelerator some PAL equations are mentioned, which i dont understand. However, these signal conversions were done in a PAL, i wish someone could point me in the right direction, so i can make them with 74xxx logic ICs.
I have allready covered all the other items mentioned, i wish you could tell me if there is something else i am missing here!
:rtfm:
Thanks