Even though I live in the UK and dont care about an NTSC MiniMig I thought that I would look into what would need to be done.
I have to say that I am not 100% upto speed on the guts of either the Amiga hardware OR MiniMig but I thought that I would have a go and perhaps Dennis would read and help correct a few things.
I think the first thing to do is to change the master clock (mclk) crystal from a 4.433619MHz PAL crystal to a 3.579545MHz NTSC one.
These crystals are standard very common, should be easy to source.
The next thing to do is change the FPGA DCM (Digital Clock Module) which is a feature of the FPGA which can create clocks with zero skew.
If you look in minimig1.v (the top level) you can see where the DCM is instantiated and thanks to Dennis's great comments you can see that all the clocks are derived from a 28MHz clock (c_28). The DCM generates this 28MHz clock by multiplying mclk by 32 and then dividing by 5.
Now that we've changed mclk to 3.579545MHz we need to change the DCM so that it generates it by multiplying by 8.
Nothing needs to change in the file minimig1.v except the comments
//Master clock generator for minimig
//This module generates all necessary clock from the 3.579545 NTSC clock
module clock_generator(mclk,c_28m,c_7m,cq_7m,e);
input mclk; //3.579545 MHz master oscillator input
output c_28m; //28.63636 MHz clock out
output c_7m; //7.15909 MHz clock out
output cq_7m; //7.15909 MHz qudrature clock out
output e; //0.715909 MHz clock enable out
reg ic_14m; //14.31818 MHz intermediate frequency
reg ic_7m;
reg icq_7m;
reg [3:0]ediv; //used to generate e clock enable
// Instantiate the DCM module
// the DCM is configured to generator c_28m from mclk (multiply by 8)
clock_dcm dcm1(
.CLKIN_IN(mclk),
.RST_IN(1'b0),
.CLKFX_OUT(c_28m),
.CLKIN_IBUFG_OUT(),
.LOCKED_OUT()
);
//generator ic_14m
always @(posedge c_28m)
ic_14m<=~ic_14m;
//generate ic_7m
always @(posedge ic_14m)
ic_7m<=~ic_7m;
//generate icq_7m
always @(negedge ic_14m)
icq_7m<=ic_7m;
//generate e
always @(posedge c_7m)
if(e)
ediv<=9;
else
ediv<=ediv-1;
assign e=(ediv==4'b0000)?1:0;
//clock buffers
BUFG buf1 ( .I(ic_7m),
.O(c_7m) );
BUFG buf2 ( .I(icq_7m),
.O(cq_7m));
endmodule
Next you have to change the DCM parameters to make it multiply by 8. The Xilinx FPGA Webpack has a GUI tool called Xilinx Architecture Wizard to do this but you can sort of get the idea if you look at the clock_dmc.v file.
You can see that you need to change the multiplier from 32 to 8 and the divider to 1. (Use the GUI in case other values need to change)
These changes alone are not be enough.
You need to change some constants (horbeam and verbeam comparisons) in agnus.v for NTSC timing. Perhaps some other register values also.
If you look in agnus.v for the module "beamcounter" this is where the constants are encoded.
Again Dennis's brilliant comments make it relatively easy to change the constants. Bear in mind when changing the constants that the clk frequency is no 7.15909MHz
I'll research the values and post the *suggested* changes here later.
