KennyR wrote:
Nah. The reason they haven't increased the external bus speed is because it doesn't actually make much difference to a PPC, as neither does the RAM speed.
The CPU’s interface to the outside world must be DDR aware for it to take advantage of DDR technologies.
A PPC does virtually all of its calculations by loading code from its registers, and there are much fewer load and store operations to external RAM.
Note that PPC does have sizable L2 cache.
The x86 needs fast RAM to work properly because of it's legacy design:
False implications. The DEC's Alpha AXP has EV6 bus way before Athlon's EV6 bus. EV6 bus is designed to 400Mhz DDR limit (without overclocking).
(VIA’s implementation of this bus is another question).
Most of AMD’s key engineers are made up of ex-DEC engineers thus their use of EV6 architecture. It's the technology they know i.e. they designed it and they built it (they also designed Hyper-transport link tech).
Lower clocked Athlons (anything below 1.4Ghz) does reasonably OK on SDRAM. One could fit an Athlon 2600+ on the KT133A based chipset (e.g. MSI-6330 V5), but the performance increase would be blunted.
Drop the anti-x86 bias. DDR has nothing to do with x86 legacy design. It's just DEC(and it's employee's skill set) has a better tech than the good old IBM.
Note that DEC was dismantled by the combine might of Compaq(now HP) and Intel.
it just doesn't have many registers and needs to hit that RAM a lot. This will always be the case.
Both the Athlon and Pentium 4 has register renaming regime to get around this problem. DDR has nothing to do with it.
Note that the modern X86 CPU does have L1 and L2 cache, not just RAM.
PPC needs a higher clockspeed and an even more optimised logic, and then it could take on the x86.
G3/G4 needs to get a deeper pipeline for clock speed.
(I recall) PowerPC 970 has ~55 million transistors and pipeline depth almost equaling the AMD’s Athlon. This CPU decode/crash 32bit PPC code before it feeds into it's executing engine (it has 9 pipelines, just like AMD's Athlon). Both the Athlon and Pentium 4 does a similar trick for X86-32 code instead of 32bit PPC code.
The proposed PPC 970 tricks around @ ~1.8Ghz just like the Athlon/Opteron.
Potentially, you could push a PPC much farther than an x86 -
Not without a deeper pipeline (faster transistors path, transistors assigned for clock speed bias, speed faster transistor switching and 'etc'). Refer to PPC 970's example.
IF the current G3/G4 can trick over 1.8Ghz why not IBM clock it to 1.8Ghz? (Why issue a new CPU core at all?)
Recall that PPC 601 is a 64bit and 32bit. I dare you clock your G3/G4 (using Apple's 1.4Ghz chips) to 2.25Ghz and lets see it survives(including the use of LN2 (i.e. liquid nitrogen) cooling.
One of the ways to test its transistors switching technology is to use LN2 cooling.
1. Athlon XP reached to +3Ghz (known)
2. Pentium 4 (Northwood) reached to ~4Ghz (known).
but sadly we'll probably never see it happen. Apple's small market share isn't enough to justify it.
Did you forget IBM's experience in regards to PPC’s clock speed increases?
Motorola/IBM is not battling with newbies in the processor design market; they are basically battling DEC** in some other form. Primarily, AMD and Microsoft (Windows NT’s creator, who also designed DEC’s VMS). To a small extent Intel, ARM, and nVidia (also made up of ex-PA-RISC people (the old HP)).
**Short for “Digital Equipment Corporation”… rumored to want a license of AmigaOS for their new Alpha CPU (back at that time). (Also known as “Digital” – “What ever it takes”/”get ready to win” marketing slogan).
