Actually, both use the same techniques.
The host processor in the A600 should be put to rest asserting BR. In the case of an A500... no processor to worry about.
Better to do a design for one, and the other one should be a modified PCB (I still think that with a bit more area, both can be done on the same PCB). That should not increase the price that much.
This is what I have in mind:
D0..D15 sould be buffered to isolate the high speed 020.
A1 to A23 should be isolated also through some '244.
Control lines should also be isolated
*UDS/*LDS should be generated. Remember that the 020 has dynamic bus sizing, so take care of SIZE0/SIZE1 and DSACK0/DSACK1.
The original Ax00 should only be accesed in the following mem areas:
0x000000..0x1fffff
0x600000..0x9fffff (A600)
0xbfd000..0xbfffff PIA (even addresses)
0xdf0000..0xffffff
*DTACK should be routed to *DSACK1 for 16 bit ports, but only in the mentioned regions.
In the Fast RAM region, should be internally generated (tyed to *AS for example, for a 3 cycle access to RAM).
I was also thinking in replacing the original Kickstart with a 32 bit version (read, with 4x8 bit epros or 2x16 bit eproms), for even faster access. That should need to get *ROMEN from the old ROM socket, or autogenerate it. But again *DSACK0/1 should be generated. If the new eproms are fast enough (could also be flash), that can be a 3 cycle access, or a 4 cycle access. A shift register can be used to generate the delayed signal.
Plenty of logic can be used to generate all this signals, may be a GAL can be cheaper, and cut on IC count, but I don't have a GAL programmer, though. I have to find a cheap GAL programmer, or make my own. I have an eprom programmer, though.
Regarding PCB costs, there is a shop in München, where they make small runs, 30 Euro (+16% VAT), each piece for 5 PCBs.
23 for 10. At 100x160 mm, 2 layers. That surface should be more than enough for this. This is the initial price, next runs are cheaper.