Assembled Minimig v1.1, larger FPGA (BGA-package)

[ThomasML]

Ok, new layout, this time I've used ISEs floorplanning tool, and I've also done synthesis and bitfile generation.

[JimS]

freqmax wrote:
Putting the MCU (pic18) inside the FPGA poses an interesting chicken-and-egg problem. It will make upgrading the FPGA flash  more cumbersome. And soldered EEPROMs have a limited number of write cycles.
The EEPROM loads the FPGA. And the FPGA can then read the flashcard. But it can't reload itself.

Yeah, a which came first situation indeed. But, if you use one of those FPGA dev boards like the XESS one you mentioned later, the flash ram is already present. The XESS board can store 4 fpga bitmaps. So it should be possible to configure the FPGA without the pic, and reserve a vhdl pic for just floppy emulation and the control panel.

[freqmax]

Regarding that XESS XSA-3S1000. Maybe the CPLD could replace the pic?, and software loaded via the DB25 parallell port?

[freqmax]

There's one possible project with a large BGA FPGA. Adding an m68k cpu. And then construct HDL code that will compare the signals of a real cpu and a HDL version.
That would allow development and improvement of such HDL m68k cpu.