FPGA for dummies

[billt]

Hi,

I'm really noob in Amiga, and I watch all this excitement around FPGA with double dutch terms for me as I'm more into software than hardware. As a matter of fact, not at all in hardware.
Can someone tell a poor ignorant what it implies for us ?
Is it something really so marvelous for the future of our platform ?
Why ? Does it concern only the game field ?

I've not used FPGAs before, but I've done a lot of silicon layout to make FPGA chips. I'm this spring taking a VHDL course at university using FPGAs. I hope to learn how to do some of my ideas.

An FPGA is a generic logic chip, which can be programmed to become a specific logic chip. You can make it become nearly any logic circuit you want. ASIC chip designers use FPGAs to prototype and debug their cictuits before spendign huge amounts of monty on ASIC fabrication masks. (kindof like camera film negatives, it's a similar usage) People cho cannot afford an ASIC production can use FPGAs in their product instead, since they are cheaper for a small quantity need. (for very large quantity needs, ASICs are far cheaper than FPGAs)

Most FPGAs today are reconfigurable while running, which means you can change part of the circuit they are behaving as. This has a benefit in that some things won't always run at the same time as each other, and you can have only one of those things loaded into the chip as it is needed, and change to the other as needed.

There are limitations, as each FPGA has a certain capacity, a circuit requiring more than a chip has to offer won't fit and needs a larger chip. But today FPGAs can hold quite a lot of things. And you can use multiple FPGAs together to increase total capacity. The other limitation is performance. It takes a lot of overhead to make an FPGA as generic and programmable as it is. To act as a simple AND gate, it will run slower than an ASIC that can simply place a single AND gate and nothing else around it. The FPGA needs to control routing through passgates and multiplexors, which slow things down compared to a simple wire in an ASIC.

To "program" an FPGA (the technically correct term is "configure") you load a bitstream file, which tells which passgates to go on or off, which way for multiplexors to select, what logic each segment will behave as (this programs a small RAM to act like logic, logic inputs go to the address bits, the output of the RAM is the logic output), and selects which flipflops are or are not used in the path, etc. Then the FPGA "is" your desired logic circuit. Some people think this is "emulation", I disagree. It's "implementation". It's not running software. It's not pretending to be an AND gate, it is an and gate. Or an Amiga500. or an Atari. Or a Commodore64. Or a Zorro to PCI bridge. Or a graphics chip. Or an ethernet controller. Or an IDE controller. Or a SCSI controller. Or an AC97 audio controller. Or...

The two big languages for FPGA designers to use are VHDL (popular in europe and US military/aerospace indsutries) and Verilog (popular in commercial US industries). You don't "compile" it, you "synthesize" it into a logic gate netlist. The gates netlist is then placed and routed into the FPGA fabric to become your desired logic chip. The FPGA does not "run" the netlist, it "becomes" the netlist. The chip does not normally change the netlist it "is" while running, the circuit it implements is what runs. Any change to the FPGA netlist is called a "reconfiguration", and once that is done, it now "is" the new circuit.

As for games, I'm not sure how it would best improve things there. It could be an FPU if you otherwise lack one. I've toyed with the idea of making an Altivec unit on a PCI card for PowerPC chips that lack one. (Sam4** for example) I'm not sure how well that would perform compared to software emulation of Altivec on a non-Altivec CPU, as things need to exit the chip, cross PCI, get into the FPGA, run at whatever speed the FPGA can give me, and go back through PCI into the CPU again. All that overhead may ruin the idea. And I have a lot to learn about microprocessor design before I try.

As for other ways we can benefit from it, we can use it as an accelerator for various things. I had an idea way back in the day to make an FPGA on a Zorro card to be a multimedia hardware codec. A reconfigurable one, so it would be a hardware MP3 decoder or encoder, or an mpeg2 video decoder or encoder, or mpeg4, or ogg vorbis, etc. for Classic machines whose 68060 just wasn't fast enough to keep up. Never made it of course, but could have been. need an encryption chip? FPGA can. There's a lot of things it can be used for.

I do think that FPGA offers a lot. I would love to see a big and fast one on a motherboard. Some Sams have a small FPGA. It's not big enough for my taste. Not does it have connections to do a lot of things. I'd like to see it multiplexed with audio connectors on the back, so it can be an audio chip. (HD Audio/Azalia anyone?) I'd like to be able to multiplex whatever VGA card I have through it, so the monitor can take the VGA card or can take something video out of the FPGA. (AGA anyone?) I'd like a lot of pins for connecting stuff up. (SCSI anyone? or Ethernet? or what else can you imagine?) I'd have done for the X1000 Xorro slot an FPGA instead of an Xmos chip, but you can probably do a lot in Xmos that you can in FPGA. But in a big fast FPGA, you could do so much more than an Xmos. (IMHO of course, as I know far more about FPGAs and only a little about Xmos. Everything I imagine using Xmos for, I could do in FPGA. Some things I imagine using FPGA for I don't think I could do in Xmos)

But for a PC-alike thing like X1000, XE, Sam460, etc. I think we'll get more use out of PCI/PCI-Express slots. Most things I'd put into FPGA are already on store shelves as PCI or PCI-Express cards.

Things like Minimig or natami or CloneA or AOocs are made for FPGAs. With enough unused space in there, you can add more. Minimig with its own native SCSI bus. Minimig with its own native SVGA (as Yaqube is doing already for FPGA-Arcade board) Minimig with FPU. Minimig with native PCI slot. Whatever you want to add, if there is capacity and usable connections, you can. (If there are not usable connections or capacity, make a new board with those connections and larger FPGA)

[billt]

Yes, very much.
But I suppose there's a bonus compared to using the original machine itself apart from the capacity of changing my system at will.
If I have a classic Amiga, is there any interest for me to get this thing ?
It seems so by reading posts about it,but I don't see why.
Will it for example allow me to connect to modern printer or network card by some trick ?

If you already have a classic Amiga you're happy with, I'm not sure Minimig etc. will change anything for you. The biggest thing you might see is performance improvement. Because FPGAs today can run a pretty fast system, you can see FPGA-Arcade or Natami implementing a CPU faster than your dedicated 680x0 chip. While some will have 68060 hard chip to start with, that is to be useful in making sure the AGA chipset and other things work well before making the internal 680x0 core. Easier to know where a bug in your design is that way, compared to "is that in my graphics chip or in my CPU?". Once the chipset cores are good, then make and debug the 680x0 core. It's expected that these internal 680x0 cores will perform faster than any hard 680x0 from Motorola/Freescale.

Also, if you don't have the fastest 68060 in your classic, then an FPGA-Arcade when it has a Minimig port including internal 680x0 may be a cheaper performance upgrade than a real classic 68060 board. it might hold more RAM than a Classic as well, though I'm not sure what the plans are for that on FPGA-Arcade or other FPGA boards.

[billt]

Is it emulation in hardware? I'm confused =)

A common question I see (not sure what it means) when it regards to FPGA is "is it cycle-exact?"

I do not consider FPGA implementations to be "emulation".

When you load the FPGA bitstream file, you are opening or closing routing connections, you are selecting inputs to multiplexors, you are telling each LUT which logic circuit it is to be (for this input value give that output value). When configuration is done, the FPGA is nto "processing" anything, it is not running software to do any of what the bitstream said. When configuration is done, the FPGA now "is" the defined circuit. All those passgates and multiplexors are now really just wires to the defined circuit. The LUTs are logic circuits. The flipflops are flipflops. There is no "emulation" which is "running" There only is a logic circuit which "is".

And the only thing that is happening is whatever your circuit is defined to do. Flipflops are flopflopping. Logic circuits are giving outputs appropriate to their inputs. Routes are wires. That's it. And there's no software or anything else operating above, below, or beside that.

If you have defined a 680x0 processor, then the 68000 processor is running 68000 software or waiting to do so. If you have defined a Zorro to PCI bus bridge, then it is converting bus cycles. If you have defined a SCSI controller, then it is controlling SCSI peripherals according to commands it receives from the host bus. If you've defined a DDR memory controller, then it is controlling DDR memory according to the host bus. That's it. If you have defined it to be an Amiga 500 with 68000 and PCI and DDR2, then it is running 68000 software, talking to PCI cards, and talking to DDR2 memory chips. Wires will clear flipflops the same way that wires clear flip-flops in custom ASIC chips. Clock signals tell flipflops to take in new values from their inputs the same way as they do in Custom ASIC chips. And gates give 1 when all inputs are 1 and otherwise 0 the same way that AND gates do in Custom ASIC chips. OR gates give a 1 output when any input is 1 value otherwise 0, same as in an ASIC. Wires conduct signals the same way as wires do in Custom ASIC chips. A 32bit CPU register is made up of 32 FPGA silicon flipflops, same as in an ASIC. Multiplexors to select datapaths in an ALU are made up of FPGA silicon multiplexors. This is hardware being routed to wire up silicon, same as logic gates are wired up in an ASIC.

It's just that the FPGA lets you change your wiring around, while an ASIC is fixed. FPGA provides a flipflop on silicon in every section. Maybe two. But it lets you skip over them if you don't want them. An FPGA can have this particular NOR gate here, or reroute and put it over there, etc. by changing which passgates are closed and which way multiplexors go. An ASIC wire is fixed by the production masks.

That's it.

In an ASIC, to connect the output of an OR gate to an inverter, you draw a wire. All silicon. In an FPGA, there are things to be OR gates and inverters on the silicon, and there's a lot of wires all over the place, which can potentially connect just about anything to anything, or disconnect anything from anything. The bitstream is read into static memory elements which control the connect or disconnect at each point, and are used to connect the various bits of silicon-level wire between your OR gate and your inverter. All hardware, all silicon.

That's it. And maybe the best way I've said it so far in this last bit.

[billt]

It is an emulation in the purest sense of the word because it's not done in silicon but simply by using instructions that are of a lower level than machine language instructions. An FPGA is just a programmable chip just like a CPU, it only serves a different purpose than a CPU.

No, it is not like a CPU. It is silicon. If I want a flipflop, that flipflop is a silicon flipflop, not a software or firmware running on some kind of processor to pretend to be a flipflop. There are not zillions of little processors laying around running some kind of code telling them how to be And gates, OR gates, Inverters or whatever. It's all silicon. I've done silicon layout of FPGA chips, I know what they look like inside, how things connect to each other, and how it all works.



Now, to decide you want an AND gate, you are not necessarily connecting to a 4-set of transistors that are exactly an AND gate and nothing else. You're connecting to a LUT, which is a small memory. The address bits of this memory are the inputs to whatever logic gate you do want, and the output of the memory is the desired output for each input set. This still is not emulation, as there is no code running. You decide what your logic truth table for this gate is, and program the output values of that truth table into this memory. Then your logic inputs select which output bit your logic demands for the current input. There's no processing there, only multiplexing to select the desired value. And after configuration, each bit is fixed. Everywhere. Back in the day it was one method of doing hardware design to use a ROM chip for a complex logic gate with lots of inputs. A ROM chip does not have a processor in it to do any emulation, it's just one way for something to "be" some logic circuit. The FPGA uses an SRAM or a fuse instead of a ROM, but it's the same principle. The LUT is a progammable logic gate, and it acts as a logic gate, and once programmed it is fixed as that logic gate until it is reprogrammed as something else or loses power. It does not have something looping on the inputs, considering what they are, and going somewhere else to look up how to respond. The LUT knows what the LUT needs to do, and it IS that. It IS logic, and it IS silicon.

Calling an FPGA an emulator is like calling a ROM chip an emulation of a ROM chip. Sounds weird huh? It makes more sense to say that a ROM chip IS a ROM chip, no? Someone might come up with a very nitpicky debate about AMD emulating an Intel chip. (going into what is x86 and what does microcode mean or do, but that also means that Intel itself makes x86 emulators, not x86 chips, and you could make an FPGA implementation of x86 that is less "emulation" than a Core i7 is)

[billt]

Of course, because that flipflop is a low level entity similar to a machine code instruction. The opcode is simply of a higher level than a flipflop.

You don't know what a flipflop is, do you? Certainly not how a flipflop compares to an opcode. (it doesn't) A flipflop is a bit. A 1 or a 0. It's held at the same value between clock edges, and only at the defined clock edge does it pass the input value to output, and hold it until next clock edge. That's 3 wires (4 if you have the negated output value as well), and maybe 6 transistors. It's a single bit storage unit. An opcode is a code, a particular value made up of 1s and 0s. It's not a storage unit. It's a command. I don't listen to my lunchbox ordering me around, do you? And the words coming out of a drill sergeant's mouth are not very useful for putting your stuff inside of are they?

I've done silicon layout of FPGA chips

Which is similar to a CPU program, only on a lower level than machine code.

The principle is the same:

With a CPU you describe your functions using high level instructions which are executed serially, while with an FPGA you describe your functions by telling the FPGA how it's gates have to be wired up, which operate in parallel, because you're describing an electronic component.

No hardwiring=emulation.

Uhm, WHAT?! You're saying that silicon layout is similar to writing a computer program? You're on some pretty wacky weed there dude. Layout is the drawing of what the silicon looks like. Drawing transistors, made up of nwell, active, P+implant, N+implant, active, poly, contacts and wires. Drawing wires between them for connections. Drawing resistors, diodes, etc. and connecting them with metal layers wiring. Red polygons, green polygons, blue polygons, tan polygons, and a variety of other colors and shades for different layers. How is that in any way comparable to writing a program? What does your crayola language do when it sees blue? Red? Yellow? I've recently been doing analog layout for an automotive chip. Not programmable, all hardwired. It's the same task, the same polygons, as drawing an FPGA. And this analog chip has no processing capability whatsoever. There's no program of any level running inside that picture of a diode. It just IS a picture of a diode. There's no program running inside a PFET. It just is a PFET. It doesn't need to go look up how to respond when the gate is a 0, it just is something that has a conncetion between the source and drain when that gates is 0. And when the gate is 1, it just is an open connection. There's no lower level than machine code running in that transistor telling things what to do, it just does.

Whether you have a single shape of blue metal1 connecting two things together, or if you have a passgate (one or two transistors) and a multiplexor (two or 4 transistors) in between, connected with metal1, metal2, metal3, metal4, etc. jumpign all over the place, it's still a connection. Electrons conduct from point A to point B. Anything in the middle is just stuff for the electron to conduct through. They get to point B and charge up the gate to a 1, or they all flow back the other direction and discharge the gate to a 0. Those electrons actually are flowing mack and forth, they're not falsely pretending to just because you say so.

[billt]

An FPGA Amiga is not an Amiga, so it must either simulate or emulate one. Whether you consider it such is irrelevant & is more related to you preferring an FPGA over an emulator.

No, it's actually related to what I know an FPGA to be before anyone puts anything at all into it.
 

The major difference between an FPGA and a software emulator is you don't have to work round operating system limitations on an FPGA. However the FPGA is still an emulator.

I guess some people really want to believe that.
 
[/quote]FPGA appears to be pretty similar to writing a computer program.[/quote]
An older way to do FPGA design is to use a schematic diagram, which was the way before HDLs came along. Is drawing a schematic diagram really the same thing as writing C or assembly code?
 
After the Minimig is working to satisfaction, and the very exact same Verilog or VHDL (or schematic) is dumped into an ASIC, which is a fixed wiring design of the exact same circuit, is that ASIC still an emulation? Is the C64DTV less of an emulator than the CommodoreOne is, since the C64DTV is a fixed ASIC compared to CommodoreOne's FPGA?

You could also go the other way and come up with a way of drawing all your different coloured polygons and turning them into a program.

I'd like to see how you'd define a language based on colored shapes and their overlap interactions with each other, and how you'd have the compiler turn them into machine code.

I understand that an FPGA is a different sort of chip, and it does come closer to the idea of emulation, and I realize that some people want to embrace it as an emulation no matter what is inside of it. I am steadfast in my believe that an FPGA is "implementation" rather than "emulation". It seems a few of you are steadfast the other way around, and I guess maybe it's best to leave it at that.

[billt]

Similar to a software emulator, the actual chips are simulated. To emulate a 68000 you'd have to dump the microcode and use that to run opcodes, using the same logic as the original chip. Nobody does that (at least not yet).

You don't "have to" use microcode in any microprocessor implementation, be it ASIC or FPGA. (Consider that a custom microprocessor design such as Motorola's original 68000, Intel's Core i7, AMD's FX, etc. are the same class as ASIC, ie very fixed hardwired stuff) It's one way to do things, and quite common, but not the only one. In a lot of processors the programmer won't have any visibility of the microcode and won't know what it looks like. Some CPUs allow access there, but others it's an invisible thing that we'll only know is even present or not if the designer tells us so.

[billt]

But if you tell the FPGA to create a gate, how does it do that?  What is the FPGAs actual method of creating a gate inside itself?  How does it remember that gate? What is actually going on at the physical level?  Surely there aren't a lot of nano-bots building and tearing down hardware inside the FPGA.

OK, but you asked for it. :p This is a bigger question that you may have realized, but fasten your seatbelts for a quick & dirty lesson in the digital logic design that an "empty" FPGA chip actually is.

I seem to have surpassed the single post character limit, so I'll try and split this into two posts.

I'll use terms such as passgate (sometimes also called transmission gate), multiplexer, LUT (lookup table), flipflop, and maybe a couple other terms which I will not define here. For those that do not already understand their definitions, I'll leave them as research topics for you, but I'll give a little description of how they are built. Read elsewhere for more in-depth descriptions. But they are very basic digital design elements.

A passgate for example can be made from a single transistor, but they are often made from two transistors in CMOS technologies. It's a very simple switch, and either connects input directly to the output, or it separates the two ends from each other. To compare with other digital logic gates, a CMOS 2-input NAND gate is made of 4 transistors. A 2-input AND gate is likely made up of 6 transistors (basically a 4-transistor NAND followed by a 2-transistor inverter).
http://www.csee.umbc.edu/courses/graduate/CMPE640/Spring07/cpatel2/lectures/lect16_combo3.pdf

A multiplexor can be made from a group of passgates, to make a sortof passive implementation, or it can be a stack of AND and OR and interter gates to make a more active output drive implementation.
http://en.wikipedia.org/wiki/Multiplexer

A flipflop (slightly more complicated than a latch) is often a loop of storage elements with passgates in between, and when the clock sets the input side passgate to open or closed, this allows the flipflop input value to overdrive a different stored value in order to have the flipflop replace its previously stored value with the current input value.
http://en.wikipedia.org/wiki/Flip-flop_(electronics)

FPGA silicon is a fixes silicon array of logic elements with a lot of fixed wires between them. Each wire is a segment, not a complete path, but it is a length of metal drawn across the silicon.

A logic element is made up of a LookUp Table (commonly shortened to LUT for less typing), one or more flipflops, and a bunch of multiplexors and passgates, and SRAMS which store your design configuration.

The LUT is a small memory with some multiplexors on the output side. When the FPGA is configured on powerup, this memory is programmed to contain the output 1 and 0 values of the logic gate you want it to become. The inputs to your logic gate control multiplexors which select a particular bit of the memory, and the value of that memory bit is your 1 or 0 output value of your logic gate. I may have said in a previous post that the address bus of this LUT memory make up your logic gate inputs. If I didn't already correct that, the address to your memory is only used during configuration of what is held inside the memory. After configuration, the contents of this LUT memory are "fixed". Most FPGAs today are made from SRAM based LUTs, so they can be reprogrammed from one power cycle to the next to do different things, and this also allows possibility of reconfiguration while the system is on and running. (see Reconfigurable Computing) Older FPGA silicon designs used fuses (or anti-fuses which close when told to do so) to set the 1 and 0 logic values, and they were typically NOT changable. If you found a bug in your circuit design, you put that buggy chip in the trash and bought a new chip. A FLASH based FPGA may have small flash memory inside your LUT instead of SRAM, or it may have a FLASH storage on-die to contain your design bitstream file to be written to SRAM based LUTs.

The inputs of your LUT logic gate control the multiplexers on the output side of the LUT memory. They select which bit of the LUT memory is connected to the ouptut signal of your overall "logic gate". The bitstream configuration determines if bit 0 contains a 1 value or a 0 value, of bit 1 contains a 1 or 0 value, if bit 2 contains a 1 or 0 value, etc. The multiplexers do not know the contents of the LUT memory, they only connect the desired LUT memory bit to the output wire.

The output of your "logic gate" LUT goes to a flipflop, perhaps directly to more than one if you want to decide between rising edge clocking or falling edge clocking or perhaps other versions of flipflops that have clear or reset controls or not. Another multiplexor will select if the direct LUT output value is the ultimate output here, or if (one of) the flipflop output is the ultimate output of this logic element. If you have clear and/or reset controls on your flipflops, then even more multiplexors are used to select which wire connects to those signals. And even other multiplexors to select which wire connects to the clock of the flipflop, and perhaps if there is an inverter to the clock or not.

The various input bits of your logic gate are connected to multiplexors which make connections to the mass of wire endpoints available to your logic element. Lets say we have a 4-bit SRAM memory as our LUT memory.

To make your logic element (LUT + multiplexors + flipflop) "become" a 2-input AND gate, which has input wires A and B, and output wire D,
multiplexer 1 chooses between bits 0 and 1 of the LUT
multiplexor 2 chooses between bits 2 and 3 of the LUT.
multiplexor 3 chooses between the outputs of multiplexwrs 1 and 2. (I wish I could draw that schematic here)
write a 0 value into bit 0 of your LUT
write a 0 value into bit 1 of your LUT
write a 0 value into bit 2 of your LUT
write a 1 value into bit 3 of your LUT

a fixed 0 value is set to control multiplexor 1, so it is fixed to connect bit 0 to its own output.
select wire A to control multiplexer 2.
select wire B to control multiplexer 3. The inputs to multiplexer 3 are the outputs from multiplexers 1 and 2.

The digital logic truth table for a 2-input AND gate is:
A B | D
0 0  | 0
0 1  | 0
1 0  | 0
1 1  | 1

Multiplexer 1 is fixed to output the value of LUT bit 0.
When wire A is a 1 value input to multiplexer2 1, then it connects bit 3 to the output of multiplexer 1. If wire A is a 0 value, then it connects bit 3 to the output of multiplexer2.

When wire B has a value of 1, it connects multiplexer 2 output to the LUT output wire C. When wire B is a 0 value, then multiplexer 3 connects the output of multiplexer 1 to wire C.

So, if wire B is 0, then the value on wire A is irrelevant. B as a 0 tells multiplexer 3 to pass multiplexer 1 to output wire C, and multiplexer wire can only select LUT bit 0, which is contains value 0. This acrees with our truth table. (we could even set LUT bit 1 to a 1 and the truth table would still be correct, since bit 1 can never get out of multiplexer 1)

If wire B is a 1, then wire A can have an affect as multiplexer 2 is connected to output wire C. If wire A is value 0, then multiplexer connects bit 2 to output wire C, meaning it connects to bit 2 value of 0 to C. If A is value 1, then multiplexer 2 connects bit 3 to output wire C, meaning it is connected to the bit 3 value of 1 to C.

 (to be continued)

[billt]

(continued form previous post)

Now, we're at point C, not the AND gate D pin. So where are we exactly? We are at a point before the flipflop, which may or may not be used. And C is actually the value input to the flipflop, and is connected to that. There is another multiplexer, let's call it multiplexer 4, which decides which signal our final D wire connects to. One input of multiplexer 4 is our C wire. The other input to multiplexer 4 is the output of the flipflop, which I'll call wire Q. For our truth table, we do not see anything like a storage element, so we will use multiplexer 4 to connect wire C to final output wire D. Wire Q coming out of the flipflop may still toggle different 1 and 0 values, but it is not connected to anything useful, and so has no noticeable affect on our logic element truth table.

Now, how do we tell multiplexer 1 that it will only ever connect bit 0 and never bit 1? How do we tell multiplexer 2 that it is controlled by wire A instead of by wire G? Or that multiplexer 3 is controlled by wire B? Or that multiplexer 4 will only ever connect wire C to wire D, and never wire Q to wire D? And how do we tell the LUT memory to contain binary value 1000 (ie [bit3,bit2,bit1,bit0])?

This is what the bitstream configuration file does. There are other SRAM memories whose outputs control the multiplexer selections. The bits of these "configuration memories" go to the select control signals on even other multiplexers. The inputs of these multiplexers are wires A, B, G, Z, W, etc. and also a fixed 1 value and a fixed 0 value, from each direction that wires come from on the chip. And one each for every input to the LUT (remember, these LUT inputs control multiplexers 1 2 and 3 for this example) And for each A, B, G, Z, W wire coning from direction N, there is a multiplexer to select which one of those sets (ie. the top side set, the bottom side set, the right side or left side set version of wire A here)

The outputs of these multiplexers are the control wires connected to multiplexers 1, 2, 3, 4, and anything else that might be in there. If you want wire A from the left side set, then you have a left side multiplexer selecting A, and you have another multiplexer selecting left side, so this signal goes through two multiplexers in order to connect to the select control on multiplexer 2 in our example. One configuration memory will tell left side multiplexer to choose A, and another configuration memory will tell the side multiplexer to choose left side. (The FPGAs I did layout for had 8-sided elements as things came diagonally as well as orthoginally.) And of course you have another chain of multiplexers to get top side wire B as the B input to our AND gate.

And the LUT memory value is written in at configuration time, same as when the other "configuration memories" are written to.

If you are not doing reconfiguration, then your design is fixed until power is lost. The configuration memory values do not change. The LUT memory values do not change. You've set your LUT to be your desired truth table, and you've set all those lots and lots of multiplexers to connect the wires how you want them connected, and now it's just an AND gate with two wires coming in and one wire going out.

The reason an ASIC will perform better than an FPGA is, well, an ASIC only needs three wires and six transistors to make an AND gate. (Ignoring the wires inside the AND gate itself to connect up those four transistors) The FPGA implementation of the AND gate has 4 big multiplexers to get A and B to the logic gate. It has two levels of multiplexers to get the desired truth table logic value on a wire, and a third level of multiplexer to say we do not want a flipflop involved. That's 5 levels of multiplexers, compared to ASIC's one level of exact AND gate. The configuration memories are static values, and they do not affect timing or performance through here. But they do take up a lot of space. As do all those multiplexers and that LUT. That's how an ASIC die can hold so much more logic than an FPGA die of the same size.

A lot of FPGA chips today are SRAM based LUT design. Not all are though. Some are antifuse, which is a permanent configuration. But other than the method to store the configuration (both LUT and multiplexer etc. selections), there's not a lot different between the two styles.

Hopefully I didn't typo anything. Let me know if there are any questions. Discuss...

[billt]

An FPGA emulates a circuit, because while the components are fixed, it's wiring is not, and therefore the circuit isn't fixed. It imitates a circuit's function by providing user definable wiring. Wires are part of a circuit, and these aren't fixed here.

Does it make a difference that, for the duration of being powered on and after writing the bitstream into the FPGA configuration memories, that the wiring and everything IS fixed until you power it off?

(ignore reconfiguration for now, as Minimig does not, the bus and memory controller on CSPPC does not, Prometheus PCI bridge, etc does not do this)

[billt]

An FPGA just removes a layer of abstraction, otherwise it's largely the same.

Please describe the layer which has been removed. Are there any additional layers below? Please describe any that remain as well as the one removed. I've tried to give as detailed an explanation of my understanding of FPGAs as I can in a lunch hour. Please do the same.

[billt]

These lookup tables are similar to SRAMs, and this is why FPGA contents is volatile.

Please discuss this detail in reference to antifuse based FPGAs.

[billt]

And there we have it: Lookup tables. This means there's no physical chip, which means it's an emulation (imitation).

Crack open my FPGA chip and put the die under a microscope. I'll point to the lookup tables. I'll point to the die. I challenge you to prove that neither is where I'm pointing to. An empty package wouldn't make a very good component for your [insert final product PCB here]...

Or perhaps it's about the meaning of the word 'emulation' being interpreted in different ways.

I think you're right there. It seems my definition of "implementation" and your definition of "emulation" are stepping on each other.

[billt]

I just mentioned SRAM-based devices because one of the posters used this to support his/her claim about FPGAs being an emulation of "real" hardware, due to their volatile nature. There are of course other non-volatile technologies as well. Apart from this I don't know what kind of answer you're fishing for here

I may have clicked reply to your message containing the original comment, rather than going in search of the original comment post to click reply to that. Mine was in response to those using SRAM as the basis of their emulation definition. If you're not that guy, sorry I got the reply wrong. Actually, i may have copy/pasted the wrong thing even. I swear I was pasting something that was more overtly SRAM == emulation than my post you refer to. Sorry, don't know how I did that.

To whoever does make the SRAM == emulation claim,
Does the lack of an SRAM in an antifuse FPGA make it less of an emulation than an SRAM FPGA, when everything other than the storage medium is pretty much the same thing?

(A blank antifuse FPGA has the potential to be just about anything. But once programmed, it really is fixed. If you want to change it, you throw that chip in the trash and buy a new blank to put the changed design into. Kindof like how some of us were changing chips on our PicassoIV graphics cards way back when)

[billt]

Sure, but you can't point to any wiring, because it doesn't exist (except for the parts that make the FPGA work as an FPGA).

Sure I can. There's a LOT of wires in there which are not part of the FPGA configuration controls. They exist only to get a signal from an output over here to an input over there. When not configured, they are floating, not connected to anything. The FPGA place and rout tool knows exactly which bits of metal are conducting each and every signal in YOUR design. The PnR tool looks at teh gates netlist for your design, and decides which bits of metal real life to connect to each other to carry YOUR signals around. There are tools for humans to see these connections and stuff too, but they tend to live only inside FPGA companies for fear that a competitor will reverse engineer their FPGA silicon design with such knowledge. If I had that tool, then we could sit down with a microscope and point to each and every bit of metal on the die that carries each and ever signal you design into it. Very real wires, very real metal atoms, very real electrons moving around in them. There aren't any ghosts lurking around in these things... Do you think that the LUTS talk to each other by telepathy or something? They need wires, very very real-life wires.