Try watching the tutorial in the help section, it'll make things a lot clearer.
In your chip, you have one silicon layer and one metal layer. There are 2 types of silicon and either kind (red for N type, yellow for P type) can act as a conductor. You only get a gate where you put one type of silicon on top of another.
You can't put 2 metal traces over the same square, nor can you put two types of silicon through the same square except where making a gate.
The only way to get two independent conductors through a square is to make one out of silicon and the other out of metal. In order to connect metal to silicon, you have to put a via point (indicated by the small circle).
The game also simulates gate delay, which becomes essential later on when you have to create delay lines and oscillators. However, if any of your designs has too much gate delay where it isn't wanted, it will fail the verification stage. meaning it is back to the drawing board.
Anyway I solved this last one I was stuck on by throwing away the idea of creating a dual NOR (which has several gates per NOR unit) based latch when I realised I could get away with just 2 gates with one feedback arranged like so:
VCC +--------+
| | |
+--NPN--PNP--+
| | |
S R Q
So simple, yet it gives the required behaviour with not more than one gate delay when setting or resetting.
