I must not get sucked into this thread....I must not get sucked into this thread...
D'Oh!
ksk wrote:
mips_proc wrote:
Really AmigaONE G4-800Mhz wins over P4 2,6Ghz, this without level3 cache?
if it where only true...
...
But it IS true. On those tiny little tings, like OGR/RC5. ;-)
The thing is, for whatever reason, the P4 does not implement certian (or maybe all) integer rotate instructions. Such things end up implemented as shifs and or'ing etc.
The RC5 client makes heavy use of these and as such, the PPC which is top dog at shift/rotate anyway, will cope rather better. Im not sure for certian, but if altivec is able to perform these instructions on sets of integer data in parallel, you can expect a big performance increase.
The thing is that these are synthetic tests. The P4 at the same clockspeed as a G4 will probably outperform it in other areas, especially in memory intensive code.
I really do think it's in IBM / Motorola's interest to haul ass and start supporting technology like DDR memory. Before anybody says that isn't a performance requirement (which frankly I doubt), just think about the price alone - DDR memory is getting cheaper than PC133 memory, simply because the PC market moves ahead so quickly and there is more demand.
What's more, the DDR capable PPC's would have less dependency on large L3 caches which would lower overall system prices further.
