Announcement concerning the Genesi/Phoenix collaboration

[MiniBobF]

That's offical confirmation that Pegasos II will run the Galileo DiscoveryII. In terms of Amiga Inc and Hyperion it's probably good news as it means it's a great deal more effort for someone to get an unlicensed copy of AmigaOS4.x running on Pegasos II.

Not only would a ROM dongle have to cracked, an additional HAL is needed, or patch/hack on the current one.

Neil Thomas, AKA MiniBobF

[MiniBobF]

I notice there is no mention of AGP at all, only PCI and PCI-X. Did I miss something when I was reading it?

If so, it seems like all the controllers are limited to older and slower PCI graphics cards.

That's possible. Unless they have someway to emulate AGP on the PCI bus? The AGP signal set is a subset of the PCI Bus. After a discussion I had with a chap on the AmigaOne mailing list, it seems the internals of an AGP device have additional registers (GART) and they lack a few features of PCI.

Unless they can find some way to emulate the AGP functionality (A skilled VHDL/ABEL programmer armed with FPGA tools could do this), then your assumption could be correct - they will be limited to PCI Graphics cards. That by no means mean they are slow though - but are modern graphics chipsets available in PCI form??

Neil Thomas, AKA MiniBobF

[MiniBobF]

Most of the difference between AGP and PCI is inside the chip, not in the bus itself. There are several techniques to bridge an AGP bus onto a PCI bus out there. I would point out that the Marvell has PCI-X, which rivals AGP 8x in speed. This means that some bandwidth can be lost in the translation process and still get top-speed AGP functionality. Even a standard PCI 64-bot 66-Mhz bus can be bridged to deliver AGP 2x speed to a peripheral card. The card doesn't *care* how the northbridge actually handles it, so long as it gets the bandwidth needed.

Yeah, but how many PCI-X graphics cards do you see available on the market??? They're either AGP or 32-bit 33MHz PCI.

Neil Thomas, AKA MiniBobF

[MiniBobF]

PCI-X 2.0 is a new, higher speed version of the conventional PCI standard, which supported signaling speeds up to 533 megatransfers per second (MTS). Revision 1.0 of the PCI-X specification defined PCI-X 66 and PCI-X 133 devices that transferred data up to 133 MTS, or over 1Gbyte per second for a 64-bit device. The present revision adds two new speed grades: PCI-X 266 and PCI-X 533, offering up to 4.3 gigabytes per second of bandwidth, 32 times faster than the first generation of PCI. Another major feature of the PCI-X 2.0 specification is enhanced system reliability. ECC support has been added both for the header and payload, providing automatic single-bit error recovery and double-bit error detection. These new standards keep pace with upcoming advances in high-bandwidth business-critical applications such as Fibre Channel, RAID, networking, InfiniBand™ Architecture, SCSI, and iSCSI.

I'm not sure I understand the question, so please forgive me if the answer isn't relevent!!

The clock for PCI-X varies depending on how many devices are on the bus.

1 device (point to point) = 133MHz
2/3 devices = 100MHz
4 or more = 66MHz

If you plug a non-PCI device in, you'll degrade the bus to 33MHz only (or 66MHz if the non-PCI device happens to be a PCI-66 Part).

Neil Thomas, AKA MiniBobF