Motorola 68060 FPGA replacement module (idea)

[Heiroglyph]

because there is m diator on amiga

Don't get me started on their driver business model...I'd almost compete out of pure spite.

[Heiroglyph]

none i remember or would seriously care for.

i think we are talking to almost drop zorro or at least zorro3, and have a direct pci interface next to amiga being interfaced by pci as well. no zorro bottleneck between cpu and pci anymore. i understand the zorro pci interface would be used to interface the remaining amiga hardware or whats left of zorro bus.

I'm just trying to replace the CPU slot connector/bus (the trapdoor or local slot on big box Amigas) with something that works with today's standards so we have the option to connect to something newer than the 060.

It would have no effect on or connect to ZorroII.

It might be smart to ignore or disable ZorroIII to simplify the design at the cost of the few cards that use it.

[Heiroglyph]

You might look for one with an EBI bus. (I htink that's what it's called) forgot about that one until today. I'm not sure what kind of selection there is though, I'm only aware of moderate performance ones between 100MHz and 200MHz which don't thrill me for this task. But I don't know much about the higher-end ARM chips.

Finding one that has that plus external interrupts with levels is tricky.

It's also not standardized across chips so you're back to vendor lock-in.

[Heiroglyph]

Interrupts can be handled by letting the Amiga side setting an interrupt register in the FPGA which in turn just signal a general interrupt (like "IRQ" on C64) to the overdrive CPU. The CPU side then reads what interrupt source that triggered the event and act accordingly. The extra performance will negate any delays for this code.

On 8086 etc.. an instruction may take 3 cycles but an IRQ may take 100 cycles just to hint on the amount of wasted cycles that may occur. Not counting Push/Pop instructions.

But if the CPU has no external interrupts, you have to poll for a signal on a GPIO constantly, which can get costly.  Am I missing something?

[Heiroglyph]

Choose another CPU

On the FPGA you can make any signal you need..

lol, I know, right?

So many CPU's are being thrown out because of IO problems though.  I'd like to maximize the options rather than being stuck with the single CPU that would ever work.

[Heiroglyph]

I'm not suggesting to use MicroBlaze soft core, I'm citing it as example of performance that can be achieved by a soft core.

That is a good point.

A couple of reasons I'm not jumping at pure FPGA:
Large fast FPGAs get really expensive.
A fast enough core hasn't been done by now, this makes me think it's excessively hard to do.
Very few people are capable of writing something that complex and efficient.  I'm not one of them.
Using an SOC gives a huge amount of devices for free, FPGA just gives a CPU.

I can help with software and smaller projects, so I'm tending to lean that direction.

If I depend on someone else to do the hardest part there's a really good chance it's not going to happen.  If I play to my strengths, I have only myself to blame if it doesn't.

[Heiroglyph]

A large enough FPGA like XC3S1600 as used in FPGA Arcade cost 68 USD at D-key. Currently it can be seen in the FPGA Arcade thread it can beat 68030 @ 20 MHz Amigas using a 16-byte cache (4.46 times A1200). With hope of 28 MHz.
Thread: http://www.amiga.org/forums/printthread.php?t=39806&pp=15&page=57
Sysinfo: http://www.yaqube.neostrada.pl/images/SysInfo28-16.gif

So XC3S1600 is more than enough and it has already been done.

The FPGA gives you any device you can imagine that can be expressed as binary gates.

I know VHDL is a bitch but so was assembler, C etc too. It's hard but the reward makes it worthwhile. The power is awesome.

I'm not really excited about 4x A1200 speeds. It's still not faster than an off the shelf 680x0 that just needs glue.

I feel that if it's not 10+ times the speed of an 060@50 then it's not a success.  If you can get 20x 060/50 performance then it's time to pat yourself on the back.  UAE can do it while also emulating the whole chipset, so it is possible with the right  CPU.

That type of speed just doesn't seem doable in a reasonably priced FPGA.

Edit: Also, like I said, *I* can't reasonably do it in an FPGA.  I can do a localbus interface and I can do software.  I'm just tired of waiting for "it's not that hard" to happen and following my gut on the quickest path to get there.

[Heiroglyph]

What's the performance like with some of these companies existing general purpose CPU cores on high-end FPGAs?  Each company seems to have one flagship CPU core.

I'd assume that they would be about as fast as could be done.  If you can beat theirs, you need to be working for them!

That should give a reasonable idea of what's even possible.

[Heiroglyph]

Sorry for throwing yet another diversion into the thread.

I don't think the PCI to Amiga warrants a separate thread unless someone makes tangible progress.

It's probably just an option for cpuXtoAmiga like FPGA 060 replacement is a subset of 680x0 accelerator.

[Heiroglyph]

I'd rather see something ship for once.

+1

[Heiroglyph]

Instruction fragmentation may occur regardless how it's implemented. Be it ARM-emulation, FPGA or ASIC.

Not if you don't mess with the instruction set.

If they all look like 680x0's then it's just a different accelerator, like GVP vs. Macrosystems vs. Phase5.

We can get plenty of speed out of hardware made in the last few decades without resorting to specialized software.

[Heiroglyph]

Adding instructions may cause fragmentation regardless of it's implementation. Reread my post

Sorry if I'm dense, are we agreeing?

I thought you implied that no matter what, fragmentation would happen.

My point was that it wouldn't fragment us unless someone added or removed 680x0 instructions.

I guess I am dense.  I can't take yes for an answer

[Heiroglyph]

Adding/removing instructions isn't going to fragment, added instructions can be ignored (see the 68020) and removed instructions can be trapped (see the 68060)... Fragmentation would occur if instruction behaviour is altered...

Reusing a previously assigned opcode cold cause problems, unless it wasn't commonly used on the Amiga... If it has potential to improve compiler code generation, or speed execution... then I say go for it!!

I disagree.  If instructions are added, then software will be written that uses them (you'll need a new compiler as well) and every other CPU will not run the software properly.

It's like the Microsoft embrace and extend tactic.  Be compatible, then add just a little change that people want to use.  Pretty soon others are obsolete and incompatible.

Higher speeds are great, but we can't afford more fragmentation.  It's just not worth a few clocks in specific situations when we can use more efficient hardware/firmware.  We're in the age of multi-GHz parts, we can get massive performance increases without resorting to a new instruction set.

If instructions are removed, but you include efficient traps with your hardware, that's fine but awkward for the user.  I absolutely hate dealing with 060 libraries.

[Heiroglyph]

TG68 source looks like a good starting point, but if Yaqube is well on the way to creating the core needed, then wouldn't it be preferred to support that goal instead of duplicating the effort? Is his project so different in FPGArcade that it wouldn't work well here? I've not followed FPGArcade very closely, will the work be open or closed source?

Plaz

With the CPU being on the same FPGA as the rest of the chips, he doesn't have to exactly duplicate the bus interface either so that's really only one part of the puzzle. (although a big one)

The A600 FPGA accelerator project is working on both bus and core, but for 68000.
http://www.majsta.com/

If the projects are both open then it's a good start.  For example, the A600 FPGA with an 020 core or use the 020 core and bolt on the A600 bus with updates to fit 680x0 bus specs.

[Heiroglyph]

While the 060 bus probably isn't the best example of something requiring obsessive-compulsive signal integrity planning, it is at the low end of where you start to care. The general rule of thumb for this starts around 50MHz. Some say they've seen problems as low as 17KHz...

I agree with everything you've said, but I have a question.

Why do we keep mentioning duplicating the 060 bus?

It's hard to find 060 CPU cards.
Real 060's have to be heavily adapted to fit the Amiga bus.

030 cards are dirt cheap and plentiful.

An 060 is no faster than a synchronous 030 with burst for communicating with the Amiga itself.  Actually they can often be slower since many 060's are async, can't burst, are running in 040 bus mode and have a lot of glue logic.

The 3000/4000 local bus are basically straight 030@25MHz, no glue required and I'd think the 1200 would be very similar but slower.  You can't talk to the Amiga faster than 25MHz, period.

Local devices on the CPU card can communicate any way you want them to.  They don't have to be limited to 030 Amiga speeds, they can be custom or off the shelf high speed buses.

030 just seems like the sweet spot for our needs.

[Heiroglyph]

Read the name of this thread's topic.

This started out as a discussion to replace the very difficult to find, legitimate, best mask-set, full-featured and fastest 68060 chips from Motorola/Freescale, to put into 68060 sockets such as the socket found on some Amiga accelerators and on MikeJ's daughtercard for FPGA-Replay system.

I understand the thread topic, but I think it's a flawed idea with a simple fix.  The 060 bus is more trouble than it is worth.  It's not the common denominator, it's an aberration.

Even 040 bus would be a better choice than 060.  Good 040 cards are really common and A3640's are like roaches.

It would be easier to make an 030 bus expansion board for the FPGA Replay and get more use out of the CPU work than just the people who are holding the remaining 060 cards for ransom.

Other things, such as the 3000/4000 accelerator slot, 030 socket, 020 socket, 000 socket, etc. have also come up, and could most likley be used via adapter, or do new PCBs directly targetting those and reuse the FPGA softcore stuff there. No reason a TG68 or N050 or whatever can't be plugged into any one of those things, but this topic came from the 68060 issue and desire to have better than whatever it is we already have.

If someone wants to pump years of work and thousands of dollars into an easily redesigned FPGA replay addon that a hand full of people own and the already hard to buy 060 cards, that's their time and money.  

It just doesn't make sense to me and I hope it doesn't take resources away from anything actually useful to the community.