A combination of the 8MByte of DRAM & an IDE interface on the same PCB would be better as an upgrade to a stock A500 or A1000. The 64Mbit +5V EDO DRAM is going to be hard to find. It may have been easier to get parts if you had used a 64Mbit SDRAM (ISSI part# IS42S16400E) with the Xilinx CPLD. Xilinx app note XAPP394 covers using a CPLD as a SDRAM controller.
