@ tnt23
What I am refering to is that a memory chip does not or appear to not have that ability but a PIC ( add-on card )does/could. I do not know of any SDRAM chips that have ability, the author did not specify that.
The author shows a counter that counts to a specified amount of time and aserts a /DTACK. The counter is started by /AS. It appears that it does not guarantee that data has made it safely.
I believe that there is a situation after so many wait-states that under the right circumstances the read/write can be repeated. That is something I have to look up.
I am not trying to say that the wait is arbitrary. Looking at the timing diagram, I believe 3 things can happen, success, bus error, or repeat.
Sure, from /AS to /DTACK is X number of cycles for which this would all happpen.
I hope this clears up what I mean.