I have a lot of XMOS dev kits in my lab; I got them before they went through their renaming kick.
The $3 part being talked about here only seems to expose the internal OTP area that used to be meant for a boot loader to load code from an SPI flash.
It has "4 logical cores" - which really are just hardware threads. The previous chips supported up to eight threads per core, and were available in 1/2/4 core variants. Only single core devices were available in TQFP, for the dual core part (each core had 64KB of ram) you needed a QFN-like pakcage, and for the four core device, you needed to go BGA.
These days, for my own designs, I mostly use the Parallax propeller.
