Motorola 68060 FPGA replacement module (idea)

[Mrs Beanbag]

You know what I don't even care about 1333MHz RAM anymore, you can buy 8Mb chips of 16-bit SRAM:
http://uk.farnell.com/renesas/r1wv6416rbg-5si/sram-64mbit-3v-55ns-48fbga/dp/2068172
I guess that would be fast enough for an off-chip cache for an FPGA 68060 implementation, if not big enough for the main ram itself.

Maybe he will shoot this down for some other reason... but if I throw enough ideas at the wall maybe one of them will stick. Like a rock.

[ChaosLord]

Confusing metaphor :crazy: When you drop a rock, it just goes faster and faster!

Then it hits your foot and stops dead.
And you start involuntarily shouting curse words.   :furious: :rant: :razz:

Ok, well, I'll take your word for it.

Just so u know, FCGAarcade/replay doesn't use modern RAM, for the above mentioned reasons.  Its really a pain to deal with.  They went back 1 iteration to RAM that is easier to deal with.  It is still more modern than the old RAM in our Amigas, but not the new stuff they use in PCs at the local store.

[ChaosLord]

You know what I don't even care about 1333MHz RAM anymore, you can buy 8Mb chips of 16-bit SRAM:
http://uk.farnell.com/renesas/r1wv6416rbg-5si/sram-64mbit-3v-55ns-48fbga/dp/2068172
I guess that would be fast enough for an off-chip cache for an FPGA 68060 implementation, if not big enough for the main ram itself.

Maybe he will shoot this down for some other reason... but if I throw enough ideas at the wall maybe one of them will stick. Like a rock.

SRAM is super easy to deal with!
Its sooooo easy to build a card or computer with SRAM.
And its super duper fast!
And it has real Random Access!

But:
Its really expensive
and drinks a lot of electricity

It is really awesome as an L2 Cache.
Or to have a bank of SRAM as your main memory for loading programs that you want to run fast.  But then things can get real complicated.

Definitely can't make a 2GB SRAM card :mickeymouse:

[freqmax]

I forgot about RAM latency, but wouldn't RAM at 1333MHz and CL9 still be able to max out a 100MHz CPU?

Would there be any advantage to using graphics memory in this application? (i.e. GDDR4/5 rather than DDR2/3)

A DRAM with the CAS latency would need 9 clock cycles before it would give you the data you requested. Ie at 133 MHz. But you also have to add RAS/CAS delays etc. Otoh you can use those 9 cycles to transfer other data. But in practice it would max out a 100 MHz CPU.

GDDR gives no real benefits in this application.

SRAM has the backside that it eats clock cycles when you least expect it. Better to deal with the real thing. Tough but true

[ChaosLord]

My original idea was to provide a solution for those that want FPGA Arcade (MikeJ) with add on board and want to make use of a fast 68060 CPU but just can't get one.

Ok so u just want whatever is the fastest 680x0 cpu u can get?

Or does it have to be exactly pin compatible to 68060?

I am not sure what you are asking for.


If u r saying u want to make a new card with an FPGA as the CPU then that would be easier.  It would be very kewl.  As the card could dedicate the whole FPGA to the CPU.

The CPU that Jens (not Schoenfeld) and Gunnar were cooking up would not even fit into the FCGAreplay.  It had really a lot of features and was really drinking up the resources.

@ChaosLord, How can you be absolutely sure there's no 1333 MHz capable RAM ..?

Fastest I ever heard about back when I studied RAM chips was 333Mhz.
On each Mhz they can send out 4 transactions if the planets and stars are aligned correctly.  For a maximum theoretical speed that gets attained every once in a while of 333*4 million memory accesses per second.

[Mrs Beanbag]

So in principle, if we were to use SRAM as memory, and FPGA as CPU at 100-ish MHz, would we still need a cache in the CPU core?

[ChaosLord]

So in principle, if we were to use SRAM as memory, and FPGA as CPU at 100-ish MHz, would we still need a cache in the CPU core?

With SRAM u either
A: Literally don't need L1 Cache
or
B: It mostly doesn't matter.

When I studied SRAM chips they seemed to go at 100Mhz.  If you get your CPU up to 120Mhz then u would lose a bit of speed.

But maybe they have 120Mhz SRAM nowadays?  (I doubt it but its possible, or maybe its extra expensive.)

Oops I think u still need cache for max speed because think of this:
Your CPU needs to process instructions and read or write results to/from memory.  That is 2 operations that need to happen simultaneously.  So u would still need at least 1 cache, the instruction cache in your previous example.  With an instruction cache it seems like u could achieve maximum speed using SRAM, even without datacache.  Hafta think about it some more tho... there could be tricks.

The kewlness of SRAM is why every Natami CPU card comes with a big bank of SRAM on it.  It was intended to eventually be configured as an L2 cache to feed the 110 Mhz 060 at super maximum speeds.

[JimDrew]

It's certainly possible to replicate any of the 68K CPUs with an FPGA.  The end result would depend on the work put into it, including the level of compatibility desired.  The 68060 would definitely be the most work due to the superscaler and pipelines. The FPU/MMU (and basic opcodes) would be pretty straight forward.  Altera makes a couple of FPGAs with sufficient internal memory that could mimic the cache.  It could all be done, but i dont think there is not enough of a market really to attract any serious developers that can do this type of work.

[freqmax]

In the FPGA Arcade schematic:
http://www.amiga.org/forums/showthread.php?t=55885&page=54
http://www.fpgaarcade.com/common/fpgaarcade_replay_b01_schematic_a2.pdf

The RAM is specified as "DDRx16-TSOP66" (46V32M16) so MEM_DQ(0..15) will transfer 16-bits on positive flank and another on the negative flank. Thus 32-bits for each clock cycle.
(PCB picture)

So that type of DDR RAM is only 2nd generation. When the current ones are at least 5th generation.

@ChaosLord, a 68060 pin compatible replacement that is code compatible and as fast as possible. No "extra" cables going places that makes you scratch your head in "not found socket" ways.
(ie not cycle exact)

[Mrs Beanbag]

I will admit an instruction cache; it can be simpler because you don't write to it. Also even a plain 68020 has an instruction cache (albeit a small one).

Just trying to think in terms of "maximum impact/minimum effort". I'm thinking essentially 68020, but fully pipelined and fastest possible clock speed.

[cunnpole]

Not quite the same, but Mike has suggested a similar approach as a backup to finding more 060s and providing an upgrade path for the Replay.

I am looking at an adapter board which will fit in the pins of the 68060 daughter board and carry either a 680x0 or a much faster Virtex7 class FPGA running a soft CPU..

http://www.amiga.org/forums/showpost.php?p=711135&postcount=1863

[freqmax]

A quick look at the 68060 technical data suggest it needs like 16 kB cache RAM. It should be possible to handle within the FPGA "BlockRAM" (as Xilinx call it). So likely no need for extra RAM. Btw, don't forget the cache coherency issues so that disc DMA and CPU don't disagree on what is in the memory..

Actually a 020 core will be smaller (I hope) and thus suffer less internal gate-to-gate latency. So it should perhaps be able to clock fast enough to outperform a 060 @ 75 MHz.

Btw, does it exist any faster than 75 MHz 68060 ..?

[psxphill]

Fastest I ever heard about back when I studied RAM chips was 333Mhz.

http://en.wikipedia.org/wiki/DDR3_SDRAM#JEDEC_standard_modules
 
It looks like 1066mhz is the fastest standard I/o clock speed & 266mhz for the memory clock speed, but the latency's are huge. This isn't a problem if you can prefetch and burst fill your cache. You get 64bits per transfer per module as well.
 
It doesn't sound like much, but compared to chip ram or the memory in your 90's accelerator. It is pretty quick.

[ChaosLord]

I will admit an instruction cache; it can be simpler because you don't write to it. Also even a plain 68020 has an instruction cache (albeit a small one).

Just trying to think in terms of "maximum impact/minimum effort". I'm thinking essentially 68020, but fully pipelined and fastest possible clock speed.

I Think I see what u r going for.

The fancy datacache did get the Natami CPU dezine team stuck for a very long time.

10  It had to be written, rewritten, rerewritten to be optimized, oops now there are a ton of bugz, oh crap this is getting really tedious I think I will take a vacation ok now where did I leave off at... oh yeah gotta fix all these bugz hold on if I rewrite it this other way it will work better when we add the MMU later lather rinse repeat  goto 10

[ChaosLord]

A quick look at the 68060 technical data suggest it needs like 16 kB cache RAM. It should be possible to handle within the FPGA "BlockRAM" (as Xilinx call it). So likely no need for extra RAM. Btw, don't forgett the cache coherency issues so that disc DMA and CPU don't disagree on what is in the memory..

All 060s, even the ones that say NO MMU, actually DO HAVE an MMU.  Its just a super simple one for marking certain blocks of memory as uncacheable.  So u can pick a block of ram that u use for DMAing things and mark it as uncacheable with the supersimple 060MMU.  So u can mark all of chipram as uncacheable.  Voila!

[freqmax]

10  It had to be written, rewritten, rerewritten to be optimized, oops now there are a ton of bugz, oh crap this is getting really tedious I think I will take a vacation ok now where did I leave off at... oh yeah gotta fix all these bugz hold on if I rewrite it this other way it will work better when we add the MMU later lather rinse repeat  goto 10

Solution, don't try everything at once. Release the source, let the crowd improve step by step by many people. Thus no overheated brain

This isn't a problem if you can prefetch and burst fill your cache.

*drumbeat* .... IF

Software has a tendency to jump all around the place..