Some interesting Altivec figures

[Kronos]

@bloodline

??
The number for the AthlonXP is about 40% higher than for the G4, and I have
a hard time believing that an 2600+ would actually runs at only 1.4GHz, the
same speed that my (1st gen) 1600XP runs at  :-o

[Hammer]

On the vast majority of tasks a modern x86 processor will crush a G4, if only because PPC systems tend to have poor infrastructure surrounding the CPU (PC133 memory, slow busses, etc).

One could compare G5 vs K8 vs K7 vs PIV EE vs PIV-C 3.2Ghz.

Note that AMD Athlons XP 2600+ can be still be installed on MSI-6330 V5 (i.e. VIA KT133A/PC133 based).

[Aragorn]

3. I’m not aware of a Barton core with a “2600+. model” number. Who knows what AMD can think of next?

My Athlon XP Barton is a 2600+
it runs at 1.92GHz

[Piru]

I've updated the KKS 7450 core to latest version. The RC5-72 result is now 10,678,428 keys/sec. The old core did 10,002,868 keys/sec.

[KennyR]

Hammer wrote:
RC5 is not the only benchmark to test for raw number-crunching abilities of the CPU and its internal cache and registers.

Why not OpenSSL benchmarks (it should fit within full size L2 cache)?

This isn't really an exercise to prove any magical superiority of PPC over x86, simply to show how powerful Altivec was in its element. RC5 just happened to be around. As Dr_Bombcrater said, it just happens to depend on how good the CPU core is for certain instructions. Thats why x86 are relatively weak at RC5 - they had many normally obscure instructions like those used for rc5 removed for better overall speed.

Oh, and isn't L2 cache external? Seems to me you can get a lot more number-crunching speed by not using external cache at all, and I think the RC5 core does fit in L1.

Anyway...

Since you know a lot about CPUs, can you answer this - why was an equivalent of Altivec not implemented in x86 cores? Was it a marketing issue (with Altivec speed boost being 'invisible' to consumers, and higher clock speed being very visible)? Was it not possible to implement? Or was it just useless?

[Aragorn]

"Oh, and isn't L2 cache external? Seems to me you can get a lot more number-crunching speed by not using external cache at all, and I think the RC5 core does fit in L1."

Depends on the processor AMD k6-2 have external level2 old pentium had external. Those slot pentium3
have sort of external level2. And PPC 604 and 603 have external level2 if they have any at all.
Dont know how it is with new PPC chips.
k6-3, Athlon(XP,64), duron, opteron, p4 all have level2 in the processor. In the case of the k6-3 since it used normal super socket7 like the k6-2 it used the cache on the moderboard as level3
 :-o

[bloodline]

Since you know a lot about CPUs, can you answer this - why was an equivalent of Altivec not implemented in x86 cores? Was it a marketing issue (with Altivec speed boost being 'invisible' to consumers, and higher clock speed being very visible)? Was it not possible to implement? Or was it just useless?
 

It is implemented in x86 CPUs, it's called MMX, MMX2, 3DNow!, SSE, and SSE2... :-)

[KennyR]

Bloodline wrote:
It is implemented in x86 CPUs, it's called MMX, MMX2, 3DNow!, SSE, and SSE2...

Boo, they were marketing gimmicks that only slowed the CPU down by adding more instructions to increase the instruction decode time per cycle. Their effect was negligible. Altivec's obviously isn't.

[bloodline]

KennyR wrote:

Bloodline wrote:
It is implemented in x86 CPUs, it's called MMX, MMX2, 3DNow!, SSE, and SSE2...

Boo, they were marketing gimmicks that only slowed the CPU down by adding more instructions to increase the instruction decode time per cycle. Their effect was negligible. Altivec's obviously isn't.

The Altivec is just an FPU that is designed to perform vector math very fast... that is what those "Marketing Gimmicks" are too...

The original Intel version of MMX sucked as it used the x87 registers, but AMD and all later varients of thses units add their own registers.

[Hammer]

KennyR wrote:

Bloodline wrote:
It is implemented in x86 CPUs, it's called MMX, MMX2, 3DNow!, SSE, and SSE2...

Boo, they were marketing gimmicks that only slowed the CPU down by adding more instructions to increase the instruction decode time per cycle. Their effect was negligible. Altivec's obviously isn't.

Actually, it does make a difference IF it done right for a certain X86 processor i.e. to remain competitive with AMD Athlon XP, Intel’s Pentium IV have rely on SSE2 code more than X87 code.

Note that PowerPC 970 has to decode or “crush” its PowerPC instructions for the relatively  new out-of-order post-RISC core.  

Pentium MMX’s design has almost zero relation to the modern  RISC86 cores.

[Hammer]

This isn't really an exercise to prove any magical superiority of PPC over x86, simply to show how powerful Altivec was in its element

One could also use PPC optimised CineBench (Beta)(MacOS) for such things.

they had many normally obscure instructions like those used for rc5 removed for better overall speed.

They could be saving on the transistor count...

Oh, and isn't L2 cache external?

Ever since Celeron 300A and most modern X86 cores has integrated L2 cache and these are;
- Pentium III
- Pentium M
- Pentium IV
- K8 Opteron/AthlonFX/Athlon64
- K7 Athlon Thunderbird (not Athlon Classic)
- K7 Athlon XP
- K7 Duron
- K6-III

One could include Intel’s Pentium Pro since it has full speed L2 cache but with two dies.  

[Hammer]

Aragorn wrote:
3. I’m not aware of a Barton core with a “2600+. model” number. Who knows what AMD can think of next?

My Athlon XP Barton is a 2600+
it runs at 1.92GHz

Sounds logical enough...

[Blitter]

It sure seems logical.  Heck my Athlon 64 FX-51 3200+ runs at a cool 2.0Ghz.

Yes it's definitly as fast as a Barton core Athlon running at 3.2Ghz like the name would describe.  but that's just in 32bit operations.  Move it to 64bit oprations and there's nothing Intel has to offer that will touch it.  The Itanium is a cludge,,, just look at the coding reviews on it.  Hell M$ of all ppl won't even embrace it and told Intel to change or suck it, basically.

[Hammer]

Blitter wrote:
It sure seems logical.  Heck my Athlon 64 FX-51 3200+ runs at a cool 2.0Ghz.

Note that "Athlon FX-51" (Sledge Hammer core) runs at 2.2Ghz, while "Athlon 64 3200+"/"3000+"(Claw Hammer core) runs at 2.0Ghz.

[Blitter]

Note that "Athlon FX-51" (Sledge Hammer core) runs at 2.2Ghz, while "Athlon 64 3200+"/"3000+"(Claw Hammer core) runs at 2.0Ghz.

You are correct, my mental fudge.

[Hammer]

Hell M$ of all ppl won't even embrace it and told Intel to change or suck it, basically.

MS Windows Anvil (AMD64 edition) is not quite ready (currently at Beta stage) for RTM status.

MS Windows Anvil is quite different to MS Windows XP Itanium Edition since Anvil is geared towards legacy and high performance gaming. MS Windows XP Itanium Edition is just geared towards PC workstations (e.g.  Itanium Deerfield base systems) type activities.